Reducing coherence-related overhead in multiprocessor systems. - Cosimo Antonio Prete; Luigi M. Ricciardi; Gianpaolo Prina (PDP, 1995)

Experiences in using a cache simulation tool in an advanced computer architecture course. - Cosimo Antonio Prete; Gianpaolo Prina (WCAE@ISCA, 1995)

A Selective Invalidation Strategy for Cache Coherence. - Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (IEICE Trans. Inf. Syst., 1995)

A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. - Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (IEEE Trans. Parallel Distributed Syst., 1995)

A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Luigi M. Ricciardi; Gianpaolo Prina (EUROMICRO, 1996)

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (HICSS (1), 1997)

Cache memory design for embedded systems based on program locality analysis. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina (MSE, 1997)

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (IEEE Concurrency, 1997)