An experimental high-density DRAM cell with a built-in gain stage. - Wonchan Kim; Joongsik Kih; Gyudong Kim; Sanghun Jung; Gijung Ahn (IEEE J. Solid State Circuits, 1994)

A CMOS serial link for fully duplexed data communication. - Kyeongho Lee; Sungjoon Kim; Gijung Ahn; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1995)

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. - Gijung Ahn; Deog-Kyoon Jeong; Gyudong Kim (IEEE J. Solid State Circuits, 2000)

A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. - Yongsam Moon; Deog-Kyoon Jeong; Gijung Ahn (IEEE J. Solid State Circuits, 2001)

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. - Sang-Hyun Lee; Moon-Sang Hwang; Youngdon Choi; Sungjoon Kim; Yongsam Moon; Bong-Joon Lee; Deog-Kyoon Jeong; Wonchan Kim; Young-June Park; Gijung Ahn (IEEE J. Solid State Circuits, 2002)

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. - Yongsam Moon; Young-Soo Park; Namhoon Kim; Gijung Ahn; Hyun J. Shin; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2004)

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. - Yongsam Moon; Gijung Ahn; Hoon Choi; Namhoon Kim; Daeyun Shim (ISSCC, 2006)