A 12-b, 10-MHz, 250-mW CMOS A/D converter. - Gil-Cho Ahn; Hee-Cheol Choi; Shin-Il Lim; Seung-Hoon Lee 006; Chul-Dong Lee (IEEE J. Solid State Circuits, 1996)

An improved algorithmic ADC clocking scheme. - Min-Gyu Kim; Gil-Cho Ahn; Un-Ku Moon (ISCAS (1), 2004)

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. - Jipeng Li; Gil-Cho Ahn; Dong-Young Chang; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. - Dong-Young Chang; Gil-Cho Ahn; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 1V 10b 30MSPS Switched-RC Pipelined ADC. - Gil-Cho Ahn; Min-Gyu Kim; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2007)

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. - Min-Gyu Kim; Gil-Cho Ahn; Pavan Kumar Hanumolu; Sanghyeon Lee; Sang-Ho Kim; Seung-Bin You; Jae-Whui Kim; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. - Young-Ju Kim; Hee-Cheol Choi; Kyung-Hoon Lee; Gil-Cho Ahn; Seung-Hoon Lee 006; Ju-Hwa Kim; Kyoung-Jun Moon; Michael Choi; Kyoung-Ho Moon; Ho-Jin Park; Byeong-Ha Park (CICC, 2009)

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration. - Seung-Hoon Lee 006; Young-Ju Kim; Hee-Cheol Choi; Gil-Cho Ahn (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 10mW stereo audio CODEC in 0.13µm CMOS. - Xicheng Jiang; Jungwoo Song; Todd Brooks; Jianlong Chen; Vinay Chandrasekhar; Felix Cheung; Sherif Galal; Darwin Cheung; Gil-Cho Ahn; Madhulatha Bonu (ISSCC, 2010)

A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. - Young-Ju Kim; Hee-Cheol Choi; Gil-Cho Ahn; Seung-Hoon Lee 006 (IEEE J. Solid State Circuits, 2010)

A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC. - Chang-Seob Shin; Min-Ho Yoon; Kang-Il Cho; Young-Ju Kim; Kwang-Soo Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (ISCAS, 2011)

A ΔΣ ADC using 4-bit SAR type quantizer for audio applications. - Jin-Seon Kim; Tae-In Kwon; Gil-Cho Ahn; Yi-Gyeong Kim; Jong-Kee Kwon (ISOCC, 2011)

A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques. - Byeong-Woo Koo; Seung-Jae Park; Gil-Cho Ahn; Seung-Hoon Lee 006 (IEICE Trans. Electron., 2011)

A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software-defined radio systems. - Hee-Cheol Choi; Pil-Seon Yoo; Gil-Cho Ahn; Seung-Hoon Lee 006 (Int. J. Circuit Theory Appl., 2011)

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique. - Chang-Seob Shin; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer. - Young-min Park; Tae-In Kwon; Kang-Il Cho; Yong-Sik Kwak; Gil-Cho Ahn; Chang-Seob Shin; Myung-Jin Lee; Seung-Bin You; Ho-Jin Park (ICECS, 2012)

A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference. - Yong-Sik Kwak; Kwang-Soo Kim; Gil-Cho Ahn (ISCAS, 2012)

A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications. - Sang-Pil Nam; Yongmin Kim; Dong-Hyun Hwang; Hyo-Jin Kim; Tai-Ji An; Jun-Sang Park; Suk-Hee Cho; Gil-Cho Ahn; Seung-Hoon Lee 006 (ISOCC, 2012)

A digitally enhanced low-distortion delta-sigma modulator for wideband application. - Jae-Hyeon Shin; Kang-Il Cho; Gil-Cho Ahn (ISOCC, 2012)

10b 150MS/s 0.4mm2 45nm CMOS ADC based on process-insensitive amplifiers. - Tai-Ji An; Jun-Sang Park; Yongmin Kim; Suk-Hee Cho; Gil-Cho Ahn; Seung-Hoon Lee 006 (ISCAS, 2013)

A 12-bit 200-kS/s SAR ADC with hybrid RC DAC. - Mi-rim Kim; Young-Ouk Kim; Yong-Sik Kwak; Gil-Cho Ahn (APCCAS, 2014)

A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (A-SSCC, 2017)

Analog front-end for EMG acquisition system. - Bum-Sik Chung; Hyeong-Kyu Kim; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn (ISOCC, 2017)

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn (IEICE Electron. Express, 2017)

A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture. - Kang-Il Cho; Yong-Sik Kwak; Ho-Jin Kim; Gil-Cho Ahn (IEICE Electron. Express, 2018)

Two CMOS time to digital converters using successive approximation register logic. - Himchan Park; Qiwei Huang; Changzhi Yu; Seulki Kim; Gil-Cho Ahn; Jinwook Burm (IEICE Electron. Express, 2018)

A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (IEEE J. Solid State Circuits, 2018)

Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's. - Tai-Ji An; Moon-Sang Hwang; Won-Jun Choe; Gil-Cho Ahn; Seung-Hoon Lee 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. - Kang-Il Cho; Yong-Sik Kwak; Ho-Jin Kim; Jun-Ho Boo; Seung-Hoon Lee 006; Gil-Cho Ahn (CICC, 2019)

A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. - Jun-Young Kil; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2019)

A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier. - Jun-Sang Park; Tai-Ji An; Gil-Cho Ahn; Seung-Hoon Lee 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. - Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Jun-Sang Park; Seung-Hoon Lee 006; Gil-Cho Ahn (A-SSCC, 2020)

A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. - Jun-Sang Park; Je-Min Jeon; Jun-Ho Boo; Jae-Hyuk Lee; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn; Seung-Hoon Lee 006 (A-SSCC, 2020)

A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. - Tae-Gwan Kim; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2020)

A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. - Yong-Sik Kwak; Ho-Jin Kim; Kang-Il Cho; Jun-Ho Boo; Gil-Cho Ahn (A-SSCC, 2021)

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. - Jun-Ho Boo; Kang-Il Cho; Ho-Jin Kim; Jae-Geun Lim; Yong-Sik Kwak; Seung-Hoon Lee 006; Gil-Cho Ahn (IEEE J. Solid State Circuits, 2021)

A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback. - Ju-Hye Han; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Jae Sang Kim; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor. - Hyoung-Jung Kim; Jae-Hyuk Lee; Jae-Geun Lim; Jun-Ho Boo; Ho-Jin Kim; Seong-Bo Park; Youngdon Choi; Jung-Hwan Choi; Gil-Cho Ahn (ISOCC, 2022)

A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC. - Mi-Ji Go; Jun-Ho Boo; Jae-Geun Lim; Hyoung-Jung Kim; Jae-Hyuk Lee; Seong-Bo Park; Byeongho Yu; Won-Jun Cho; Gil-Cho Ahn (ISOCC, 2023)

A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer. - Seong-Bo Park; Jun-Ho Boo; Jae-Geun Lim; Hyoung-Jung Kim; Jae-Hyuk Lee; Won-Jun Cho; Gil-Cho Ahn (ISOCC, 2023)

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. - Ho-Jin Kim; Jun-Ho Boo; Kang-Il Cho; Yong-Sik Kwak; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A CMOS Analog Front-End for Hall Sensor Readout IC. - Kang-Il Cho; Jun-Ho Boo; Jae-Geun Lim; Gil-Cho Ahn (ICEIC, 2024)

A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition. - Jae-Geun Lim; Jun-Ho Boo; Hyoung-Jung Kim; Jae-Hyuk Lee; Kang-Il Cho; Gil-Cho Ahn (ICEIC, 2025)