A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (ETS, 2010)

On using a SPICE-like TSTAC™ eFlash model for design and test. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (DDECS, 2011)

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (J. Electron. Test., 2012)

Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory Arrays. - Viktor Markov; Gilles Festes; Louisa Schneider; Steven Lemke; Serguei Jourba; Alexander Kotov (IMW, 2023)

Analog Tuning of Floating-Gate Cells with Sub-Elementary Charge Accuracy for In-Memory Computing Applications. - Yuri Tkachev; Steven Lemke; Louisa Schneider; Gilles Festes; Parviz Ghazavi (IMW, 2023)

Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG. - Ralf Richter; Stefan Dünkel; Bert Müller; Frank Mauersberger; Sven Wittek; Sven Beyer; Jana Böhme; Uwe Ritter; Violetta Sessi; Zhen Xu; Maximilian Drescher; Jinho Kim; et al. (IMW, 2024)