Clock-Delayed Domino for Adder and Combinational Logic Desig. - Gin Yee; Carl Sechen (ICCD, 1996)

Domino logic synthesis using complex static gates. - Tyler Thorp; Gin Yee; Carl Sechen (ICCAD, 1998)

Design and Synthesis of Monotonic Circuits. - Tyler Thorp; Gin Yee; Carl Sechen (ICCD, 1999)

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. - Fabian Klass; Chaim Amir; Ashutosh Das; Kathirgamar Aingaran; Cindy Truong; Richard Wang; Anup Mehta; Raymond A. Heald; Gin Yee (IEEE J. Solid State Circuits, 1999)

Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. - Jovanka Ciric; Gin Yee; Carl Sechen (DATE, 2000)

Output Prediction Logic: A High-Performance CMOS Design Technique. - Larry McMurchie; Su Kio; Gin Yee; Tyler Thorp; Carl Sechen (ICCD, 2000)

An Automated Shielding Algorithm and Tool For Dynamic Circuits. - Gin Yee; Tyler Thorp; Ron Christopherson; Ban P. Wang; Carl Sechen (ISQED, 2000)

A third-generation SPARC V9 64-b microprocessor. - Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; Michael Ang; Michael Boland; Pankaj Dixit; Gary Gouldsberry; Dale Greenley; Joel Grinberg; Jason M. Hart; Tim Horel; Wen-Jay Hsu; et al. (IEEE J. Solid State Circuits, 2000)

Clock-delayed domino for dynamic circuit design. - Gin Yee; Carl Sechen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Locally clocked pipelines and dynamic logic. - Gregg N. Hoyer; Gin Yee; Carl Sechen (IEEE Trans. Very Large Scale Integr. Syst., 2002)