Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. - J. A. López; Ginés Doménech; R. Ruiz; Tom J. Kazmierski (ISCAS (4), 2002)

Current Mode CMOS Synthesis of a Motor-Control Neural System. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Hans Hauer; José Ángel Díaz-Madrid (IWANN (2), 2003)

Empirical Model Generations of Microwave Devices Exploiting Linear Regression Models. - Ginés Doménech; Juan Hinojosa; Juan Martínez-Alajarín; F. Javier Garrigós (ISCC, 2005)

Empirical Model Optimization of Microwave Devices Exploiting Genetic Algorithms. - F. Javier Garrigós; Juan Hinojosa; Juan Martínez-Alajarín; Ginés Doménech (ISCC, 2005)

Description and Simulation of Bio-inspired Systems Using VHDL-AMS. - Ginés Doménech-Asensi; José-Alejandro López Alcantud; Ramón Ruiz Merino (IWINAC (2), 2005)

Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. - Ginés Doménech-Asensi; Juan Martínez-Alajarín; Ramón Ruiz Merino; José-Alejandro López Alcantud (FPL, 2006)

Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications. - Juan Hinojosa; Ginés Doménech-Asensi (ECCTD, 2007)

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. - José Ángel Díaz-Madrid; Pedro Monsalve-Campillo; Juan Hinojosa; María Victoria Rodellar Biarge; Ginés Doménech-Asensi (IWINAC (2), 2007)

A behavioral model development methodology for microwave components and integration in VHDL-AMS. - Ginés Doménech-Asensi; Juan Hinojosa; Juan Martínez-Alajarín (Microelectron. J., 2007)

Accurate and reusable macromodeling technique using a fuzzy-logic approach. - Ginés Doménech-Asensi; Juan Hinojosa; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2008)

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. - José Ángel Díaz-Madrid; Harald Neubauer; Hans Hauer; Ginés Doménech-Asensi; Ramón Ruiz Merino (DATE, 2009)

Fuzzy logic technique for accurate analog circuits macromodel sizing. - José Ángel Díaz-Madrid; Juan Hinojosa; Ginés Doménech-Asensi (Int. J. Circuit Theory Appl., 2010)

A secure energy-efficient m-banking application for mobile devices. - María-Dolores Cano; Ginés Doménech-Asensi (J. Syst. Softw., 2011)

A fourth order CMOS band pass filter for PIR sensors. - Ginés Doménech-Asensi; F. Martinez-Viviente; J. Illade-Quinteiro; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; Juan Martínez-Alajarín; Francisco J. Fernández-Luque; Juan M. Carrillo; Miguel Angel Domínguez (ICECS, 2012)

A system for ubiquitous fall monitoring at home via a wireless sensor network and a wearable mote. - Roberto Paoli; Francisco J. Fernández-Luque; Ginés Doménech; Félix Martínez; Juan Zapata-Pérez; Ramón Ruiz (Expert Syst. Appl., 2012)

Voltage boosters for on-chip solar cells on focal-plane processors. - Víctor M. Brea 001; Manuel Suarez; J. Illade-Quinteiro; Paula López 001; Diego Cabello; Ginés Doménech-Asensi (ICECS, 2013)

An energy efficient middleware for an ad-hoc AAL wireless sensor network. - Francisco J. Fernández-Luque; David Pérez; Félix Martínez; Ginés Doménech; Isabel Navarrete; Juan Zapata-Pérez; Ramón Ruiz (Ad Hoc Networks, 2013)

Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. - Ginés Doménech-Asensi; José Ángel Díaz-Madrid; Ramón Ruiz Merino (Int. J. Circuit Theory Appl., 2013)

Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. - Pablo Leyva; Ginés Doménech-Asensi; F. Javier Garrigós; Julio Illade-Quinteiro; Víctor M. Brea 001; Paula López 001; Diego Cabello (FPL, 2014)

Ambient assisted living system with capacitive occupancy sensor. - Francisco J. Fernández-Luque; Félix L. Martínez; Ginés Doménech; Juan Zapata-Pérez; Ramón Ruiz (Expert Syst. J. Knowl. Eng., 2014)

Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise. - Julio Illade-Quinteiro; Víctor M. Brea 001; Paula López Martinez 001; Diego Cabello; Ginés Doménech-Asensi (Sensors, 2015)

Proactive Intelligent System for Optimizing Traffic Signaling. - Ramon Sanchez-Iborra; Juan F. Inglés-Romero; Ginés Doménech-Asensi; José-Luis Moreno-Cegarra; María-Dolores Cano (DASC/PiCom/DataCom/CyberSciTech, 2016)

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; José-Alejandro López Alcantud; M. Oberst (ISCAS, 2017)

Generation of new power processing structures exploiting genetic programming. - Ginés Doménech-Asensi; Tom J. Kazmierski (ISIE, 2017)

Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. - Ricardo Carmona-Galán; Jorge Fernández-Berni; Ángel Rodríguez-Vázquez; Paula López Martinez 001; Víctor Manuel Brea Sánchez; Diego Cabello Ferrer; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez (ICDSC, 2018)

Traffic Metrics at Urban Intersections using a Low-Cost Image Processing Approach. - Juan Francisco Inglés-Romero; Ginés Doménech-Asensi; María-Dolores Cano-Baños; Víctor Morales-Esteras (ICDSC, 2018)

FPGA real time synthesis of simplified SIFT algorithm. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (ICDSC, 2018)

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. - Pablo Rubio-Ibáñez; Ramón Ruiz Merino; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; José Ángel Díaz-Madrid; José-Alejandro López Alcantud (Int. J. Circuit Theory Appl., 2018)

Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. - Ginés Doménech-Asensi; Tom J. Kazmierski (FDL, 2019)

An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. - Ginés Doménech-Asensi; Tom J. Kazmierski (ISCAS, 2019)

Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (ISCAS, 2019)

High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. - Ginés Doménech-Asensi; Tom J. Kazmierski (DATE, 2020)

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Javier Martínez 001 (ISCAS, 2020)

Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. - Ginés Doménech-Asensi; Tom J. Kazmierski (ISCAS, 2020)

All-hardware SIFT implementation for real-time VGA images feature extraction. - Ginés Doménech-Asensi; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Víctor Manuel Brea Sánchez; Paula López 001 (J. Real Time Image Process., 2020)

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (DCIS, 2021)

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; Ramón Ruiz Merino (Circuits Syst. Signal Process., 2021)

On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices. - Ginés Doménech-Asensi; María-Dolores Cano; Víctor Morales-Esteras (J. Signal Process. Syst., 2022)

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Ángel Díaz-Madrid (ISCAS, 2023)

Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods. - Ginés Doménech-Asensi; Tom J. Kazmierski (Circuits Syst. Signal Process., 2024)

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez (J. Real Time Image Process., 2024)

Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. - Ginés Doménech-Asensi; Francisco Javier Andreo-Oliver; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2025)