Reconciling security with virtualization: A dual-hypervisor design for ARM TrustZone. - Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo; Anup Patel (ICIT, 2018)

Towards the Hypervision of Hardware-based Control Flow Integrity for Arm Platforms. - Giulia Ferri; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (ITASEC, 2019)

AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC. - Francesco Restuccia 002; Alessandro Biondi 001; Mauro Marinoni; Giorgiomaria Cicero; Giorgio C. Buttazzo (DAC, 2020)

A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems. - Alessandro Biondi 001; Federico Nesti; Giorgiomaria Cicero; Daniel Casini; Giorgio C. Buttazzo (IEEE Embed. Syst. Lett., 2020)

Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems. - Daniel Casini; Alessandro Biondi 001; Giorgiomaria Cicero; Giorgio C. Buttazzo (RTAS, 2021)

A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving. - Luca Belluardo; Andrea Stevanato; Daniel Casini; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (RTCSA, 2021)

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms. - Alessandro Biondi 001; Daniel Casini; Giorgiomaria Cicero; Niccolò Borgioli; Giorgio C. Buttazzo; Gaetano Patti; Luca Leonardi; Lucia Lo Bello; Marco Solieri; Paolo Burgio; Ignacio Sanudo Olmedo; Angelo Ruocco; et al. (IEEE Access, 2021)

PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms. - Gabriele Serra; Pietro Fara; Giorgiomaria Cicero; Francesco Restuccia 002; Alessandro Biondi 001 (RTAS, 2022)

Profiling and controlling I/O-related memory contention in COTS heterogeneous platforms. - Matteo Zini; Giorgiomaria Cicero; Daniel Casini; Alessandro Biondi 001 (Softw. Pract. Exp., 2022)

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems. - Niccolò Borgioli; Matteo Zini; Daniel Casini; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Supporting AI-powered real-time cyber-physical systems on heterogeneous platforms via hypervisor technology. - Edoardo Cittadini; Mauro Marinoni; Alessandro Biondi 001; Giorgiomaria Cicero; Giorgio C. Buttazzo (Real Time Syst., 2023)

Integrating the Simplex Architecture to Enhance Safety in Deep Learning Autonomous Systems. - Niko Salamini; Federico Nesti; Mauro Marinoni; Giorgiomaria Cicero; Gabriele Serra; Alessandro Biondi 001; Giorgio C. Buttazzo (ICCPS, 2025)

A Design Flow to Securely Isolate FPGA Bus Transactions in Heterogeneous SoCs. - Niko Salamini; Sara Alonso Salazar; Gabriele Serra; Giorgiomaria Cicero; Pietro Fara; Federico Aromolo; Alessandro Biondi 001 (RTAS, 2025)