Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. - Giorgos Dimitrakopoulos; Dimitris Nikolos; Dimitris Bakalis (IOLTW, 2002)

A Family of Parallel-Pre.x Modulo 2n - 1 Adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ASAP, 2003)

Efficient modulo 2n+1 tree multipliers for diminished-1 operands. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (ICECS, 2003)

Virtual-scan: a novel approach for software-based self-testing of microprocessors. - Giorgos Dimitrakopoulos; Xrysovalantis Kavousianos; Dimitris Nikolos (ISCAS (5), 2003)

A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ISCAS (5), 2003)

Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. - Giorgos Dimitrakopoulos; Pavlos Kolovos; P. Kalogerakis; Dimitris Nikolos (PATMOS, 2004)

A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. - Giorgos Dimitrakopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

New architectures for modulo 2N - 1 adders. - Giorgos Dimitrakopoulos; Dimitris G. Nikolos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ICECS, 2005)

Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. - Giorgos Dimitrakopoulos; Dimitris Nikolos (PATMOS, 2005)

High-Speed Parallel-Prefix VLSI Ling Adders. - Giorgos Dimitrakopoulos; Dimitris Nikolos (IEEE Trans. Computers, 2005)

Efficient Diminished-1 Modulo 2^n+1 Multipliers. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (IEEE Trans. Computers, 2005)

An Energy-Delay Efficient Subword Permutation Unit. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (ASAP, 2006)

Fast bit permutation unit for media enhanced microprocessors. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (ISCAS, 2006)

Sorter Based Permutation Units for Media-Enhanced Microprocessors. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. - Nikos Chrysos; Giorgos Dimitrakopoulos (Hot Interconnects, 2008)

Fast arbiters for on-chip network switches. - Giorgos Dimitrakopoulos; Nikos Chrysos; Costas Galanopoulos (ICCD, 2008)

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. - Giorgos Dimitrakopoulos; Costas Galanopoulos; Christos Mavrokefalidis; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Practical High-Throughput Crossbar Scheduling. - Nikos Chrysos; Giorgos Dimitrakopoulos (IEEE Micro, 2009)

A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric. - Yiouli Kritikou; Giorgos Dimitrakopoulos; E. Dimitrellou; Panagiotis Demestichas (Telematics Informatics, 2009)

Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks. - Giorgos Dimitrakopoulos; Christoforos Kachris; Emmanouil Kalligeros (FPL, 2011)

Switch allocator for bufferless network-on-chip routers. - Giorgos Dimitrakopoulos; Kostas Galanopoulos (INA-OCMC@HiPEAC, 2011)

Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches. - Giorgos Dimitrakopoulos; Emmanouil Kalligeros (DATE, 2012)

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. - Antoni Roca 001; José Flich; Giorgos Dimitrakopoulos (FPL, 2012)

Low-cost fault-tolerant switch allocator for network-on-chip routers. - Giorgos Dimitrakopoulos; Emmanouil Kalligeros (INA-OCMC@HiPEAC, 2012)

On Modulo 2^n+1 Adder Design. - Haridimos T. Vergos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2012)

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. - Darío Suárez Gracia; Giorgos Dimitrakopoulos; Teresa Monreal Arnal; Manolis Katevenis; Víctor Viñals Yúfera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Switch folding: network-on-chip routers with time-multiplexed output ports. - Giorgos Dimitrakopoulos; N. Georgiadis; Chrysostomos Nicopoulos; Emmanouil Kalligeros (DATE, 2013)

Merged Switch Allocation and Traversal in Network-on-Chip Switches. - Giorgos Dimitrakopoulos; Emmanouil Kalligeros; Costas Galanopoulos (IEEE Trans. Computers, 2013)

Hardware primitives for the synthesis of multithreaded elastic systems. - Giorgos Dimitrakopoulos; I. Seitanidis; Anastasios Psarras; K. Tsiouris; Pavlos M. Mattheakis; Jordi Cortadella (DATE, 2014)

ElastiStore: An elastic buffer architecture for Network-on-Chip routers. - I. Seitanidis; Anastasios Psarras; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (DATE, 2014)

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture. - I. Seitanidis; Anastasios Psarras; Emmanouil Kalligeros; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (NOCS, 2014)

Editorial. - Davide Bertozzi; Giorgos Dimitrakopoulos; Sören Sonntag (Des. Autom. Embed. Syst., 2014)

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation. - Anastasios Psarras; I. Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (DATE, 2015)

Timing-resilient Network-on-Chip architectures. - Alexandros Panteloukas; Anastasios Psarras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IOLTS, 2015)

The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. - Davide Bertozzi; Giorgos Dimitrakopoulos; José Flich; Sören Sonntag (Des. Autom. Embed. Syst., 2015)

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip. - Ioannis Seitanidis; Anastasios Psarras; Kypros Chrysanthou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2015)

CrossOver: Clock domain crossing under virtual-channel flow control. - Michalis Paschou; Anastasios Psarras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (DATE, 2016)

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. - Anastasios Psarras; Junghee Lee; Pavlos M. Mattheakis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ACM Great Lakes Symposium on VLSI, 2016)

RapidLink: A network-on-chip architecture with double-data-rate links. - Anastasios Psarras; Savvas Moisidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ICECS, 2016)

Powermax: an automated methodology for generating peak-power traffic in networks-on-chip. - Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (NOCS, 2016)

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. - Kypros Chrysanthou; Panayiotis Englezakis; Andreas Prodromou; Andreas Panteli; Chrysostomos Nicopoulos; Yiannakis Sazeides; Giorgos Dimitrakopoulos (ACM Trans. Archit. Code Optim., 2016)

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing. - Anastasios Psarras; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2016)

PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. - Anastasios Psarras; Junghee Lee; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (DAC, 2017)

Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling. - Monobrata Debnath; Dimitris Konstantinou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos; Wei-Ming Lin; Junghee Lee (AISTECS@HiPEAC, 2017)

Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project. - Emmanuel Karampasis; Nick P. Papanikolaou; Dionisis Voglitsis; Michael Loupis; Anastasios Psarras; Alexandros Boubaris; Dimitris Baros; Giorgos Dimitrakopoulos (IEEE Access, 2017)

A Dual-Clock Multiple-Queue Shared Buffer. - Anastasios Psarras; Michalis Paschou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2017)

Networks-on-Chip With Double-Data-Rate Links. - Anastasios Psarras; Savvas Moisidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Low-power dual-edge-triggered synchronous latency-insensitive systems. - Dimitris Konstantinou; Anastasios Psarras; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (MOCAST, 2018)

A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. - Karyofyllis Patsidis; Dimitris Konstantinou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (Microprocess. Microsystems, 2018)

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. - Ron Gabor; Yiannakis Sazeides; Arkady Bramnik; Alexandros Andreou; Chrysostomos Nicopoulos; Karyofyllis Patsidis; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DATE, 2019)

Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage. - Zacharias Takakis; Dimitrios Mangiras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IVSW, 2019)

Multi-Armed Bandits for Autonomous Timing-driven Design Optimization. - Apostolos Stefanidis; Dimitrios Mangiras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (PATMOS, 2019)

Timing-Driven and Placement-Aware Multibit Register Composition. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Automatic Generation of Peak-Power Traffic for Networks-on-Chip. - Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). - Yiannakis Sazeides; Arkady Bramnik; Ron Gabor; Chrysostomos Nicopoulos; Ramon Canal; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DFT, 2020)

Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. - Theodoros Panagiotis Chatzinikolaou; Iosif-Angelos Fyrigos; Rafailia-Eleni Karamani; Vasileios G. Ntinas; Giorgos Dimitrakopoulos; Sorin Cotofana; Georgios Ch. Sirakoulis (ISCAS, 2020)

SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers. - Dimitrios Konstantinou; Chrysostomos Nicopoulos; Junghee Lee; Georgios Ch. Sirakoulis; Giorgos Dimitrakopoulos (ISCAS, 2020)

RISC-V2: A Scalable RISC-V Vector Processor. - Karyofyllis Patsidis; Chrysostomos Nicopoulos; Georgios Ch. Sirakoulis; Giorgos Dimitrakopoulos (ISCAS, 2020)

Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. - Dimitrios Mangiras; Pavlos M. Mattheakis; Pierre-Olivier Ribet; Giorgos Dimitrakopoulos (ISPD, 2020)

Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. - Apostolos Stefanidis; Dimitrios Mangiras; Chrysostomos Nicopoulos; David G. Chinnery; Giorgos Dimitrakopoulos (ISPD, 2020)

Memristive Learning Cellular Automata: Theory and Applications. - Rafailia-Eleni Karamani; Iosif-Angelos Fyrigos; Vasileios G. Ntinas; Orestis Liolis; Giorgos Dimitrakopoulos; Mustafa Altun; Andrew Adamatzky; Mircea R. Stan; Georgios Ch. Sirakoulis (MOCAST, 2020)

Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering. - Dimitrios Mangiras; Apostolos Stefanidis; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

The Mesochronous Dual-Clock FIFO Buffer. - Dimitrios Konstantinou; Anastasios Psarras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment. - Dimitrios Mangiras; Giorgos Dimitrakopoulos (MOCAST, 2021)

Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching. - Dimitris Konstantinou; Chrysostomos Nicopoulos; Junghee Lee; Giorgos Dimitrakopoulos (Integr., 2021)

Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. - Apostolos Stefanidis; Dimitrios Mangiras; Chrysostomos Nicopoulos; David G. Chinnery; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Sum Propagate Adders. - Giorgos Dimitrakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2021)

FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks. - Christodoulos Peltekis; Dionysios Filippas; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ASAP, 2022)

LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride. - Dionysios Filippas; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ISVLSI, 2022)

IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. - Yiannakis Sazeides; Alex Gerber; Ron Gabor; Arkady Bramnik; George Papadimitriou 001; Dimitris Gizopoulos; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos; Karyofyllis Patsidis (MICRO, 2022)

Virtual-Channel Flow Control Across Mesochronous Clock Domains. - Giorgos Dimitrakopoulos; Anastasios Psarras; Chrysostomos Nicopoulos (MOCAST, 2022)

Low-Cost Online Convolution Checksum Checker. - Dionysios Filippas; Nikolaos Margomenos; Nikolaos Mitianoudis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. - Dionysios Filippas; Christodoulos Peltekis; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (AICAS, 2023)

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. - Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos; Dionisios N. Pnevmatikatos (DATE, 2023)

Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification. - Giorgos Dimitrakopoulos; E. Kallitsounakis; Z. Takakis; A. Stefanidis; Chrysostomos Nicopoulos (MOCAST, 2023)

Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. - Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (MOCAST, 2023)

The Case for Asymmetric Systolic Array Floorplanning. - Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos; Chrysostomos A. Nicopoulos (CoRR, 2023)

Exploiting data encoding and reordering for low-power streaming in systolic arrays. - Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (Microprocess. Microsystems, 2023)

Streaming Dilated Convolution Engine. - Dionysios Filippas; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Task-Based Parallel Programming for Gate Sizing. - Dimitrios Mangiras; David G. Chinnery; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Synthesis of Approximate Parallel-Prefix Adders. - Apostolos Stefanidis; Ioanna Zoumpoulidou; Dionysios Filippas; Giorgos Dimitrakopoulos; Georgios Ch. Sirakoulis (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Reusing Softmax Hardware Unit for GELU Computation in Transformers. - Christodoulos Peltekis; Kosmas Alexandridis; Giorgos Dimitrakopoulos (AICAS, 2024)

Error Checking for Sparse Systolic Tensor Arrays. - Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos (AICAS, 2024)

IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. - Vasileios Titopoulos; Kosmas Alexandridis; Christodoulos Peltekis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (DATE, 2024)

Comparative Analysis and Implementation of HTTP3, MQTT, and CoAP for IoT Applications. - Dimitris Koutras; Giorgos Dimitrakopoulos; Vangelis Malamas; Panayiotis Kotzanikolaou; Christos Douligeris (PCI, 2024)

A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators. - Dionysios Filippas; Christodoulos Peltekis; Vasileios Titopoulos; Ioannis Kansizoglou; Georgios Ch. Sirakoulis; Antonios Gasteratos; Giorgos Dimitrakopoulos (IEEE Access, 2024)

DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. - Christodoulos Peltekis; Vasileios Titopoulos; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Comput. Archit. Lett., 2024)

Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines. - Kosmas Alexandridis; Christodoulos Peltekis; Dionysios Filippas; Giorgos Dimitrakopoulos (CoRR, 2024)

Online Alignment and Addition in Multi-Term Floating-Point Adders. - Kosmas Alexandridis; Giorgos Dimitrakopoulos (CoRR, 2024)

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs. - Vasileios Titopoulos; George Alexakis; Kosmas Alexandridis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (CF, 2025)

Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators. - Kosmas Alexandridis; Vasileios Titopoulos; Giorgos Dimitrakopoulos (ISVLSI, 2025)

Efficient Implementation of RISC-V Vector Permutation Instructions. - Vasileios Titopoulos; George Alexakis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ISVLSI, 2025)

Periodic Online Testing for Sparse Systolic Tensor Arrays. - Christodoulos Peltekis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (MOCAST, 2025)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors. - Vasileios Titopoulos; Kosmas Alexandridis; Christodoulos Peltekis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2025)

Online Alignment and Addition in Multiterm Floating-Point Adders. - Kosmas Alexandridis; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2025)

FLASH-D: FlashAttention with Hidden Softmax Division. - Kosmas Alexandridis; Vasileios Titopoulos; Giorgos Dimitrakopoulos (CoRR, 2025)

High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic. - George Alexakis; Dimitrios Schoinianakis; Giorgos Dimitrakopoulos (CoRR, 2025)

Custom Algorithm-based Fault Tolerance for Attention Layers in Transformers. - Vasileios Titopoulos; Kosmas Alexandridis; Giorgos Dimitrakopoulos (CoRR, 2025)

GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks. - Christodoulos Peltekis; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)