Compiling custom instructions onto expression-grained reconfigurable architectures. - Paolo Bonzini; Giovanni Ansaloni; Laura Pozzi 001 (CASES, 2008)

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. - Giovanni Ansaloni; Paolo Bonzini; Laura Pozzi 001 (SASP, 2008)

Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. - Giovanni Ansaloni; Paolo Bonzini; Laura Pozzi 001 (DATE, 2009)

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. - Giovanni Ansaloni; Laura Pozzi 001; Kazuyuki Tanimura; Nikil D. Dutt (DATE, 2011)

EGRA: A Coarse Grained Reconfigurable Architectural Template. - Giovanni Ansaloni; Paolo Bonzini; Laura Pozzi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Embedded real-time ECG delineation methods: A comparative evaluation. - Rubén Braojos; Giovanni Ansaloni; David Atienza; Francisco J. Rincón (BIBE, 2012)

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities). - Marios Milis; Kyriacos Michaelides; Anastasis Kounoudes; Giovanni Ansaloni; David Atienza; Frédéric Giroud; Pierre-François Ruedi; Frederic Masson (BIBE, 2012)

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. - Giovanni Ansaloni; Kazuyuki Tanimura; Laura Pozzi 001; Nikil D. Dutt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A methodology for embedded classification of heartbeats using random projections. - Rubén Braojos; Giovanni Ansaloni; David Atienza (DATE, 2013)

Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. - Ahmed Yasir Dogan; Rubén Braojos; Jeremy Constantin; Giovanni Ansaloni; Andreas Burg 001; David Atienza (DATE, 2013)

Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring. - Frédéric Giroud; Pascal Persechini; Pierre-François Ruedi; Giovanni Ansaloni; Rubén Braojos; F. Viemon; Frederic Masson (BioCAS, 2014)

Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach. - Jelena Milosevic; Andreas Dittrich; Alberto Ferrante; Miroslaw Malek; Camilo Rojas Quiros; Rubén Braojos; Giovanni Ansaloni; David Atienza (CinC, 2014)

Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. - Rubén Braojos; Hossein Mamaghanian; Alair Dias Junior; Giovanni Ansaloni; David Atienza; Francisco J. Rincón; Srinivasan Murali (DAC, 2014)

Hardware/software approach for code synchronization in low-power multi-core sensor nodes. - Rubén Braojos; Ahmed Yasir Dogan; Ivan Beretta; Giovanni Ansaloni; David Atienza (DATE, 2014)

Power-efficient joint compressed sensing of multi-lead ECG signals. - Hossein Mamaghanian; Giovanni Ansaloni; David Atienza; Pierre Vandergheynst (ICASSP, 2014)

Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes. - Rubén Braojos; Ivan Beretta; Giovanni Ansaloni; David Atienza (Sensors, 2014)

Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. - Soumya Basu 002; Pablo García Del Valle; Georgios Karakonstantis; Giovanni Ansaloni; David Atienza (ISVLSI, 2015)

A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. - Loris Duch; Soumya Basu 002; Rubén Braojos; David Atienza; Giovanni Ansaloni; Laura Pozzi 001 (BioCAS, 2016)

PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms. - Daniele Bortolotti; Andrea Bartolini; Luca Benini; V. Rajesh Pamula 002; Nick Van Helleputte; Chris Van Hoof; Marian Verhelst; Tobias Gemmeke; Rubén Braojos Lopez; Giovanni Ansaloni; David Atienza; Pierre Vandergheynst (Conf. Computing Frontiers, 2016)

Nano-engineered architectures for ultra-low power wireless body sensor nodes. - Rubén Braojos; David Atienza; Mohamed M. Sabry Aly; Tony F. Wu; H.-S. Philip Wong; Subhasish Mitra; Giovanni Ansaloni (CODES+ISSS, 2016)

Inexact-aware architecture design for ultra-low power bio-signal analysis. - Soumya Basu 002; Pablo García Del Valle; Georgios Karakonstantis; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (IET Comput. Digit. Tech., 2016)

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing. - Rubén Braojos; Daniele Bortolotti; Andrea Bartolini; Giovanni Ansaloni; Luca Benini; David Atienza (IEEE Trans. Computers, 2017)

HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. - Loris Duch; Soumya Basu 002; Rubén Braojos; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. - Soumya Basu 002; Loris Duch; Rubén Braojos; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (ACM Trans. Embed. Comput. Syst., 2017)

A partitioning strategy for exploring error-resilience in circuits: work-in-progress. - Ilaria Scarabottolo; Giovanni Ansaloni; Laura Pozzi 001 (CASES, 2018)

Circuit carving: A methodology for the design of approximate hardware. - Ilaria Scarabottolo; Giovanni Ansaloni; Laura Pozzi 001 (DATE, 2018)

Lattice-Traversing Design Space Exploration for High Level Synthesis. - Lorenzo Ferretti; Giovanni Ansaloni; Laura Pozzi 001 (ICCD, 2018)

Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. - Georgios Zacharopoulos; Andrea Barbon; Giovanni Ansaloni; Laura Pozzi 001 (HPCS, 2018)

Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. - Soumya Basu 002; Loris Duch; Miguel Peón-Quirós; David Atienza; Giovanni Ansaloni; Laura Pozzi 001 (ISCAS, 2018)

Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. - Ilaria Scarabottolo; Giovanni Ansaloni; George A. Constantinides; Laura Pozzi 001 (DAC, 2019)

Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. - Lorenzo Ferretti; Giovanni Ansaloni; Laura Pozzi 001; Amir Aminifar; David Atienza; Leila Cammoun; Philippe Ryvlin (DATE, 2019)

Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. - Georgios Zacharopoulos; Lorenzo Ferretti; Giovanni Ansaloni; Giuseppe Di Guglielmo; Luca P. Carloni; Laura Pozzi 001 (ICCD, 2019)

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. - Loris Duch; Soumya Basu 002; Miguel Peón-Quirós; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (IEEE Embed. Syst. Lett., 2019)

RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. - Georgios Zacharopoulos; Lorenzo Ferretti; Emanuele Giaquinta; Giovanni Ansaloni; Laura Pozzi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. - Giovanni Ansaloni; Ilaria Scarabottolo; Laura Pozzi 001 (ARC, 2020)

Approximate Logic Synthesis: A Survey. - Ilaria Scarabottolo; Giovanni Ansaloni; George A. Constantinides; Laura Pozzi 001; Sherief Reda (Proc. IEEE, 2020)

Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. - Lorenzo Ferretti; Jihye Kwon; Giovanni Ansaloni; Giuseppe Di Guglielmo; Luca P. Carloni; Laura Pozzi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). - Joshua Alexander Harrison Klein; Alexandre Levisse; Giovanni Ansaloni; David Atienza; Marina Zapater; Martino Dazzi; Geethan Karunaratne; Irem Boybat; Abu Sebastian; Davide Rossi; Francesco Conti 001; Elana Pereira de Santana; et al. (CF, 2021)

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. - William Andrew Simon; Valérian Ray; Alexandre Levisse; Giovanni Ansaloni; Marina Zapater; David Atienza (DAC, 2021)

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. - Marco Rios; Flavio Ponzina; Giovanni Ansaloni; Alexandre Levisse; David Atienza (DATE, 2021)

A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. - Flavio Ponzina; Marco Rios; Giovanni Ansaloni; Alexandre Levisse; David Atienza (ISVLSI, 2021)

DB4HLS: A Database of High-Level Synthesis Design Space Explorations. - Lorenzo Ferretti; Jihye Kwon; Giovanni Ansaloni; Giuseppe Di Guglielmo; Luca P. Carloni; Laura Pozzi 001 (IEEE Embed. Syst. Lett., 2021)

Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. - Lorenzo Ferretti; Giovanni Ansaloni; Laura Pozzi 001 (IEEE Trans. Emerg. Top. Comput., 2021)

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs. - Flavio Ponzina; Miguel Peón-Quirós; Giovanni Ansaloni; David Atienza (COINS, 2022)

INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. - Lorenzo Ferretti; Giovanni Ansaloni; Renaud Marquis; Tomás Teijeiro; Philippe Ryvlin; David Atienza; Laura Pozzi 001 (DATE, 2022)

Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. - Halima Najibi; Alexandre Levisse; Giovanni Ansaloni; Marina Zapater; David Atienza (ACM Great Lakes Symposium on VLSI, 2022)

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. - Marco Rios; Flavio Ponzina; Giovanni Ansaloni; Alexandre Levisse; David Atienza (ACM Great Lakes Symposium on VLSI, 2022)

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures. - Rafael Medina 001; Joshua Kein; Yasir Mahmood Qureshi; Marina Zapater; Giovanni Ansaloni; David Atienza (LASCAS, 2022)

A Soft SIMD Based Energy Efficient Computing Microarchitecture. - Pengbo Yu; Alexandre Levisse; Mohit Gupta 004; Timon Evenblij; Giovanni Ansaloni; Francky Catthoor; David Atienza (CoRR, 2022)

A Hardware/Software Co-Design Vision for Deep Learning at the Edge. - Flavio Ponzina; Simone Machetti; Marco Rios; Benoît Walter Denkinger; Alexandre Levisse; Giovanni Ansaloni; Miguel Peón-Quirós; David Atienza (IEEE Micro, 2022)

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. - Ilaria Scarabottolo; Giovanni Ansaloni; George A. Constantinides; Laura Pozzi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers. - Alireza Amirshahi; Joshua Alexander Harrison Klein; Giovanni Ansaloni; David Atienza (ASP-DAC, 2023)

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. - Rafael Medina 001; Joshua Kein; Giovanni Ansaloni; Marina Zapater; Sergi Abadal; Eduard Alarcón; David Atienza (ASP-DAC, 2023)

An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing. - Rubén Rodríguez Álvarez; Benoît W. Denkinger; Juan Sapriza; Jose Angel Miranda Calero; Giovanni Ansaloni; David Atienza Alonso (CF, 2023)

Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. - Michael T. Niemier; Xiaobo Sharon Hu; Liu Liu; Mohammad Mehdi Sharifi; Ian O'Connor; David Atienza; Giovanni Ansaloni; Can Li; Asif Khan; Daniel C. Ralph (DATE, 2023)

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. - Grégoire Eggermann; Marco Rios; Giovanni Ansaloni; Sani R. Nassif; David Atienza (VLSI-SoC, 2023)

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal. - Rafael Medina 001; Darong Huang; Giovanni Ansaloni; Marina Zapater; David Atienza (VLSI-SoC, 2023)

Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. - Halima Najibi; Alexandre Levisse; Giovanni Ansaloni; Marina Zapater; Miroslav Vasic; David Atienza (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. - Marco Rios; Flavio Ponzina; Alexandre Levisse; Giovanni Ansaloni; David Atienza (IEEE Trans. Emerg. Top. Comput., 2023)

ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. - Joshua Alexander Harrison Klein; Irem Boybat; Yasir Mahmood Qureshi; Martino Dazzi; Alexandre Levisse; Giovanni Ansaloni; Marina Zapater; Abu Sebastian; David Atienza (IEEE Trans. Computers, 2023)

Event-based sampled ECG morphology reconstruction through self-similarity. - Silvio Zanoli; Giovanni Ansaloni; Tomás Teijeiro; David Atienza (Comput. Methods Programs Biomed., 2023)

Overflow-free Compute Memories for Edge AI Acceleration. - Flavio Ponzina; Marco Rios; Alexandre Levisse; Giovanni Ansaloni; David Atienza (ACM Trans. Embed. Comput. Syst., 2023)

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. - Ian O'Connor; Sara Mannaa; Alberto Bosio; Bastien Deveautour; Damien Deleruyelle; Tetiana Obukhova; Cédric Marchand 002; Jens Trommer; Çigdem Çakirlar; Bruno Neckel Wesling; Thomas Mikolajick; Oskar Baumgartner; et al. (DATE, 2024)

Resource-Efficient Continual Learning for Personalized Online Seizure Detection. - Amirhossein Shahbazinia; Flavio Ponzina; Jose Angel Miranda; Jonathan Dan; Giovanni Ansaloni; David Atienza (EMBC, 2024)

Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. - Alireza Amirshahi; Giovanni Ansaloni; David Atienza (PARMA-DITAM, 2024)

Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware. - Anna Burdina; Gabriel Catel Torres; Pasquale Davide Schiavone; Miguel Peón-Quirós; Giovanni Ansaloni; David Atienza; Marina Zapater (ISLPED, 2024)

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD. - Pengbo Yu; Flavio Ponzina; Alexandre Levisse; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Francky Catthoor (ISVLSI, 2024)

LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles. - Corey Lammie; Flavio Ponzina; Yuxuan Wang 003; Joshua Alexander Harrison Klein; Marina Zapater; Irem Boybat; Abu Sebastian; Giovanni Ansaloni; David Atienza (CoRR, 2024)

MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots. - Alireza Amirshahi; Maedeh H. Toosi; Siamak Mohammadi; Stefano Albini; Pasquale Davide Schiavone; Giovanni Ansaloni; Amir Aminifar; David Atienza (CoRR, 2024)

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. - Pengbo Yu; Flavio Ponzina; Alexandre Levisse; Mohit Gupta 004; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2024)

SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. - Cristian Tirelli; Juan Sapriza; Rubén Rodríguez Álvarez; Lorenzo Ferretti; Benoît W. Denkinger; Giovanni Ansaloni; Jose Angel Miranda; David Atienza; Laura Pozzi 001 (ACM J. Emerg. Technol. Comput. Syst., 2024)

Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures. - Rafael Medina 001; Giovanni Ansaloni; Marina Zapater; Alexandre Levisse; Saeideh Alinezhad Chamazcoti; Timon Evenblij; Dwaipayan Biswas; Francky Catthoor; David Atienza (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An MLIR-Based Compilation Framework for CGRA Application Deployment. - Yuxuan Wang 003; Cristian Tirelli; Lara Orlandic; Juan Sapriza; Rubén Rodríguez Álvarez; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (ARC, 2025)

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions. - Maxime Henri Aspros; Juan Sapriza; Giovanni Ansaloni; David Atienza (CF (Companion), 2025)

HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge. - Pedro Palacios; Rafael Medina 001; Giovanni Ansaloni; David Atienza (CF (Companion), 2025)

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems. - Pedro Palacios; Rafael Medina 001; Jean-Luc Rouas; Giovanni Ansaloni; David Atienza (ACM Great Lakes Symposium on VLSI, 2025)

A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces. - Natalia Martínez; Juan Sapriza; Pasquale Davide Schiavone; Giovanni Ansaloni; Luke Bashford; Andrew Jackson 001; David Atienza; Timothy G. Constandinou (ISCAS, 2025)

Keep All in Memory with Maxwell: A Near-SRAM Computing Architecture for Edge AI Applications. - Grégoire Eggermann; Giovanni Ansaloni; David Atienza (ISQED, 2025)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications. - Simone Machetti; Pasquale Davide Schiavone; Giovanni Ansaloni; Miguel Peón-Quirós; David Atienza (ISVLSI, 2025)

ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors. - Yuxuan Wang 003; Lara Orlandic; Simone Machetti; Giovanni Ansaloni; David Atienza (IEEE Trans. Biomed. Circuits Syst., 2025)

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications. - Simone Machetti; Pasquale Davide Schiavone; Lara Orlandic; Darong Huang; Deniz Kasap; Giovanni Ansaloni; David Atienza (CoRR, 2025)

Towards Accurate RISC-V Full System Simulation via Component-Level Calibration. - Karan Pathak; Joshua Alexander Harrison Klein; Giovanni Ansaloni; Said Hamdioui; Georgi Gaydadjiev; Marina Zapater; David Atienza (ACM Trans. Embed. Comput. Syst., 2025)

An MLIR-based Compilation Framework for Control Flow Management on CGRAs. - Yuxuan Wang 003; Cristian Tirelli; Giovanni Ansaloni; Laura Pozzi 001; David Atienza (CoRR, 2025)

Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes. - Lorenzo Ruotolo; Lara Orlandic; Pengbo Yu; Moritz Brunion; Daniele Jahier Pagliari; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Julien Ryckaert; Francky Catthoor; Yukai Chen (CoRR, 2025)