Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs. - Giovanni Brignone; M. Usman Jamal; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2022)

A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs. - Giovanni Brignone; Mihai T. Lazarescu; Luciano Lavagno (ICCD, 2023)

To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration. - Fabrizio Ottati; Chang Gao 002; Qinyu Chen; Giovanni Brignone; Mario R. Casu; Jason K. Eshraghian; Luciano Lavagno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. - Roberto Bosio; Giovanni Brignone; Filippo Minnella; M. Usman Jamal; Luciano Lavagno (DATE, 2024)

Low-Power Subgraph Isomorphism at the Edge Using FPGAs. - Roberto Bosio; Giovanni Brignone; Teodoro Urso; Mihai T. Lazarescu; Luciano Lavagno; Paolo Pasini (IEEE Access, 2025)

Making acceleration more amenable with novel high-level synthesis techniques for FPGAs. - Giovanni Brignone (2025)

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators. - Giovanni Brignone; Roberto Bosio; Fabrizio Ottati; Claudio Sansoè; Luciano Lavagno (ACM Trans. Reconfigurable Technol. Syst., 2025)