Estimating the efficiency of collaborative problem-solving, with applications to chip design. - Mary Y. L. Wisniewski; Emmanuel Yashchin; Robert L. Franch; David P. Conrady; Giovanni Fiorenza; I. Cevdet Noyan (IBM J. Res. Dev., 2003)

The physical design of on-chip interconnections. - Mary Y. L. Wisniewski; Emmanuel Yashchin; Robert L. Franch; David P. Conrady; Daniel N. Maynard; Giovanni Fiorenza; I. Cevdet Noyan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Assessment of on-chip wire-length distribution models. - Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. - Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. - Gerald G. Lopez; Giovanni Fiorenza; Thomas J. Bucelot; Phillip J. Restle; Mary Yvonne Lanzerotti (ACM Great Lakes Symposium on VLSI, 2005)

Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. - Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand (SLIP, 2005)

Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements. - Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand (IBM J. Res. Dev., 2005)

Impact of interconnect length changes on effective materials properties (dielectric constant). - Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand (SLIP, 2007)

New simulation methodology for effects of radiation in semiconductor chip structures. - Henry H. K. Tang; Conal E. Murray; Giovanni Fiorenza; Kenneth P. Rodbell; Michael S. Gordon; David F. Heidel (IBM J. Res. Dev., 2008)