6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI. - Giovanni Steffan; Emanuele Depaoli; Enrico Monaco; Nicolo Sabatino; Walter Audoglio; Augusto Andrea Rossi; Simone Erba; Matteo Bassi; Andrea Mazzanti (ISSCC, 2017)

A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. - Emanuele Depaoli; Enrico Monaco; Giovanni Steffan; Marco Mazzini; Hongyang Zhang; Walter Audoglio; Oscar Belotti; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Andrea Mazzanti (ISSCC, 2018)

Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. - Andrea Bandiziol; Werner Grollitsch; Giovanni Steffan; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)