Mobile CPU power/performance benchmarking and process technology co-optimization. - Robert Bucki; Todd Bridges; Benjamin Bowers; T. Xue; I. Mir; D. Le; T. Kazi; Jeff Fischer; Samit Ekbote; S. Sengupta; G. Nallapati (ICICDT, 2014)

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. - Seung Chul Song; J. Xu; D. Yang; K. Rim; P. Feng; Jerry Bao; J. Zhu; Joseph Wang; G. Nallapati; Mustafa Badaroglu; Praneeth Narayanasetti; B. Bucki; et al. (VLSI Circuits, 2016)

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. - Alvin Leng Sun Loke; Da Yang 007; Tin Tin Wee; Jonathan L. Holland; Patrick Isakanian; Kern Rim; Sam Yang; Jacob S. Schneider; Giri Nallapati; Sreeker Dundigal; Hasnain Lakdawala; Behnam Amelifard; et al. (CICC, 2019)

High Performance 5G Mobile SOC Productization with 4nm EUV Fin-FET Technology. - Jun Yuan; Jie Deng; Vicki Lin; Ying Chen; Joseph Chiu; Minghuei Lin; Jun Chen; Deedee Zhang; Yukai Chen; David Liu; Bo Yu; Hao Wang; et al. (VLSI Technology and Circuits, 2023)