A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator. - Harbinder Singh; James Beausang; Girish Patankar (ITC, 1997)

Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach. - Hillol Maity; Kaushik Khatua; Santanu Chattopadhyay; Indranil Sengupta 001; Girish Patankar; Parthajit Bhattacharya (ICIT, 2019)

A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis. - Kaushik Khatua; Hillol Maity; Santanu Chattopadhyay; Indranil Sengupta 001; Girish Patankar; Parthajit Bhattacharya (TENCON, 2019)

A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing. - Hillol Maity; Kaushik Khatua; Santanu Chattopadhyay; Indranil Sengupta 001; Girish Patankar; Parthajit Bhattacharya (ISDCS, 2020)