3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. - Hugh Mair; Ericbill Wang; Alice Wang; Ping Kao; Yuwen Tsai; Sumanth Gururajarao; Rolf Lagerquist; Jin Son; Gordon Gammie; Gordon Lin; Achuta Thippana; Kent Li; et al. (ISSCC, 2017)

An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range. - Sandipan Sinha; Manish Trivedi; Jaswinder Singh; Sriharsha Enjapuri; Deepesh Gujjar; Ramesh Halli; Girishankar Gurumurthy (APCCAS, 2023)

A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range. - Sandipan Sinha; Manish Trivedi; Jaswinder Singh; Sriharsha Enjapuri; Deepesh Gujjar; Ramesh Halli; Girishankar Gurumurthy (VLSID, 2024)