Incremental formal design verification. - Gitanjali Swamy; Robert K. Brayton (ICCAD, 1994)

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. - Adnan Aziz; Vigyan Singhal; Gitanjali Swamy; Robert K. Brayton (ICCD, 1994)

Incremental methods for FSM traversal. - Gitanjali Swamy; Robert K. Brayton; Vigyan Singhal (ICCD, 1995)

VIS: A System for Verification and Synthesis. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (CAV, 1996)

VIS. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (FMCAD, 1996)

Formal Verification of Digital Systems. - Gitanjali Swamy (VLSI Design, 1997)

Efficient Verification and Synthesis using Design Commonalities. - Gitanjali Swamy; Stephen A. Edwards; Robert K. Brayton (VLSI Design, 1998)