3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC, 2012)

Configurable Low-Latency Interconnect for Multi-core Clusters. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC (Selected Papers), 2012)

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. - Giulia Beanato; Paolo Giovannini; Alessandro Cevrero; Panagiotis Athanasopoulos; Michael Zervas; Yuksel Temiz; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. - Tiansheng Zhang; Alessandro Cevrero; Giulia Beanato; Panagiotis Athanasopoulos; Ayse K. Coskun; Yusuf Leblebici (DATE, 2013)

3D serial TSV link for low-power chip-to-chip communication. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (ICICDT, 2014)

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. - Giulia Beanato; Kiarash Gharibdoust; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)