Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. - Giuliano Sisto; Peter Debacker; Rongmei Chen; Geert Van der Plas; Richard Chou; Eric Beyne; Dragomir Milojevic (3DIC, 2019)

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). - Giuliano Sisto; Rongmei Chen; Richard Chou; Geert Van der Plas; Eric Beyne; Rod Metcalfe; Dragomir Milojevic (SLIP, 2021)

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. - Rongmei Chen; Giuliano Sisto; Odysseas Zografos; Dragomir Milojevic; Pieter Weckx; Geert Van der Plas; Eric Beyne (SLIP, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. - Giuliano Sisto; Odysseas Zografos; Bilal Chehab; Naveen Kakarla; Yang Xiang; Dragomir Milojevic; Pieter Weckx; Geert Hellings; Julien Ryckaert (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. - Mohamed Naeim; Hanqi Yang; Pinhong Chen; Rong Bao; Antoine Dekeyser; Giuliano Sisto; Moritz Brunion; Rongmei Chen; Geert Van der Plas; Eric Beyne; Dragomir Milojevic (3DIC, 2023)

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. - Giuliano Sisto; R. Preston; Rongmei Chen; Gioele Mirabelli; Anita Farokhnejad; Yun Zhou; Ivan Ciofi; Anne Jourdain; A. Veloso; Michele Stucchi; Odysseas Zografos; Pieter Weckx; et al. (VLSI Technology and Circuits, 2023)

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. - Nesara Eranna Bethur; Pruek Vanna-Iampikul; Odysseas Zografos; Lingjun Zhu; Giuliano Sisto; Dragomir Milojevic; Alberto García Ortiz; Geert Hellings; Julien Ryckaert; Francky Catthoor; Sung Kyu Lim (DAC, 2024)

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. - Yun Zhou; S. C. Song; Halil Kükner; Giuliano Sisto; Sheng Yang; Anita Farokhnejad; Mohamed Naeim; Moritz Brunion; Ji-Yung Lin; Odysseas Zografos; Pieter Weckx; Shashank Ekbote; et al. (VLSI Technology and Circuits, 2024)

Energon: A Sustainability-Driven Modeling Framework for AI Data Centers. - Wenzhe Guo; Joyjit Kundu; Uras Tos; Giuliano Sisto; Cedric Rolin; Lars-Åke Ragnarsson; Timon Evenblij (ISPASS, 2025)

System-performance and cost modeling of Large Language Model training and inference. - Wenzhe Guo; Joyjit Kundu; Uras Tos; Weijiang Kong; Giuliano Sisto; Timon Evenblij; Manu Perumkunnil (CoRR, 2025)