MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Daniele Rolfo; Paolo Prinetto (Asian Test Symposium, 2011)

A unifying formalism to support automated synthesis of SBSTs for embedded caches. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Daniele Rolfo; Paolo Prinetto (EWDTS, 2011)

Validation & Verification of an EDA automated synthesis tool. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Daniele Rolfo; Paolo Prinetto (IDT, 2011)

An area-efficient 2-D convolution implementation on FPGA for space applications. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Daniele Rolfo; Gabriele Tiotto; Paolo Prinetto (IDT, 2011)

A software-based self test of CUDA Fermi GPUs. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Ippazio Martella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (ETS, 2013)

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (FPL, 2013)

FEMIP: A high performance FPGA-based features extractor & matcher for space applications. - Stefano Di Carlo; Giulio Gambardella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta; Piergiorgio Lanza (FPL, 2013)

ZipStream: Improving dependability in dynamic partial reconfiguration. - Stefano Di Carlo; Giulio Gambardella; Trong Huynh Bao; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (IDT, 2013)

SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications. - Stefano Di Carlo; Giulio Gambardella; Piergiorgio Lanza; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (IDT, 2013)

Increasing the robustness of CUDA Fermi GPU-based systems. - Stefano Di Carlo; Giulio Gambardella; Marco Indaco; Ippazio Martella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (IOLTS, 2013)

Fault mitigation strategies for CUDA GPUs. - Stefano Di Carlo; Giulio Gambardella; Ippazio Martella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (ITC, 2013)

On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems. - Stefano Di Carlo; Giulio Gambardella; Paolo Prinetto; Frank Reichenbach; Trond Løkstad; Gulzaib Rafiq (DSD, 2014)

A novel methodology to increase fault tolerance in autonomous FPGA-based systems. - Stefano Di Carlo; Giulio Gambardella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta; Alessandro Vallero (IOLTS, 2014)

A cloud-based Cyber-Physical System for environmental monitoring. - Teodora Sanislav; George Dan Mois; Silviu Folea; Liviu Miclea; Giulio Gambardella; Paolo Prinetto (MECO, 2014)

Dynamic partial reconfiguration for dependable systems. - Giulio Gambardella (2014)

SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs. - Stefano Di Carlo; Giulio Gambardella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (ACM Trans. Reconfigurable Technol. Syst., 2015)

SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications. - Stefano Di Carlo; Giulio Gambardella; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. - Yaman Umuroglu; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Philip Heng Wai Leong; Magnus Jahre; Kees A. Vissers (FPGA, 2017)

Scaling Binarized Neural Networks on Reconfigurable Logic. - Nicholas J. Fraser; Yaman Umuroglu; Giulio Gambardella; Michaela Blott; Philip Heng Wai Leong; Magnus Jahre; Kees A. Vissers (PARMA-DITAM@HiPEAC, 2017)

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu; Miriam Leeser (ICCD, 2017)

Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. - Julian Faraone; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Philip Heng Wai Leong (ICONIP (2), 2017)

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. - Jiang Su; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Gianluca Durelli; David B. Thomas; Philip Heng Wai Leong; Peter Y. K. Cheung (ARC, 2018)

Inference of quantized neural networks on heterogeneous all-programmable devices. - Thomas B. Preußer; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott (DATE, 2018)

Customizing Low-Precision Deep Neural Networks for FPGAs. - Julian Faraone; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott; Philip H. W. Leong; David Boland (FPL, 2018)

FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. - Vladimir Rybalkin; Alessandro Pappalardo; Muhammad Mohsin Ghaffar; Giulio Gambardella; Norbert Wehn; Michaela Blott (FPL, 2018)

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu (CoRR, 2018)

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu; Miriam Leeser; Kees A. Vissers (ACM Trans. Reconfigurable Technol. Syst., 2018)

Efficient Error-Tolerant Quantized Neural Network Accelerators. - Giulio Gambardella; Johannes Kappauf; Michaela Blott; Christoph Doehring; Martin Kumm; Peter Zipf; Kees A. Vissers (DFT, 2019)

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. - Yifan Yang; Qijing Huang 001; Bichen Wu; Tianjun Zhang; Liang Ma 003; Giulio Gambardella; Michaela Blott; Luciano Lavagno; Kees A. Vissers; John Wawrzynek; Kurt Keutzer (FPGA, 2019)

Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. - Michaela Blott; Johannes Kath; Lisa Halder; Yaman Umuroglu; Nicholas J. Fraser; Giulio Gambardella; Miriam Leeser; Linda Doyle (FPGA, 2020)

FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. - Ussama Zahid; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott; Kees A. Vissers (ITC, 2020)

Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. - Michaela Blott; Nicholas J. Fraser; Giulio Gambardella; Lisa Halder; Johannes Kath; Zachary Neveu; Yaman Umuroglu; Alina Vasilciuc; Miriam Leeser; Linda Doyle (IEEE Trans. Computers, 2021)

On the RTL Implementation of FINN Matrix Vector Compute Unit. - Syed Asad Alam; David Gregg; Giulio Gambardella; Michael Preußer; Michaela Blott (CoRR, 2022)

Fault-Tolerant Neural Network Accelerators With Selective TMR. - Timoteo García Bertoa; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott; John McAllister (IEEE Des. Test, 2023)

On the RTL Implementation of FINN Matrix Vector Unit. - Syed Asad Alam; David Gregg; Giulio Gambardella; Thomas B. Preußer; Michaela Blott (ACM Trans. Embed. Comput. Syst., 2023)

On the Fault Sensitivity of Natural Language Embeddings Computation. - Sumeet Sapkal; Ussama Zahid; Giulio Gambardella; Haralampos-G. Stratigopoulos; Brian Clerkin (ETS, 2025)