A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops. - Giuseppe Natale; Giulio Stramondo; Pietro Bressana; Riccardo Cattaneo; Donatella Sciuto; Marco D. Santambrogio (ICCAD, 2016)

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration. - Amit Kulkarni 002; Poona Bahrebar; Dirk Stroobandt; Giulio Stramondo; Catalin Bogdan Ciobanu; Ana Lucia Varbanescu (FPT, 2017)

Towards Application-Centric Parallel Memories. - Giulio Stramondo; Catalin Bogdan Ciobanu; Ana Lucia Varbanescu; Cees de Laat (Euro-Par Workshops, 2018)

MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs. - Catalin Bogdan Ciobanu; Giulio Stramondo; Cees de Laat; Ana Lucia Varbanescu (IPDPS Workshops, 2018)

EXTRA: an open platform for reconfigurable architectures. - Catalin Bogdan Ciobanu; Giulio Stramondo; Ana Lucia Varbanescu; Andreas Brokalakis; Antonis Nikitakis; Lorenzo Di Tucci; Marco Rabozzi; Luca Stornaiuolo; Marco D. Santambrogio; Grigorios Chrysos 001; Charalampos Vatsolakis; Georgios Charitopoulos; et al. (SAMOS, 2018)

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS. - Luca Stornaiuolo; Marco Rabozzi; Marco D. Santambrogio; Donatella Sciuto; Catalin Bogdan Ciobanu; Giulio Stramondo; Ana Lucia Varbanescu (VLSI-SoC (Selected Papers), 2018)

HLS Support for Polymorphic Parallel Memories. - Luca Stornaiuolo; Marco Rabozzi; Donatella Sciuto; Marco D. Santambrogio; Giulio Stramondo; Catalin Bogdan Ciobanu; Ana Lucia Varbanescu (VLSI-SoC, 2018)

μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration. - Giulio Stramondo; Manil Dev Gomony; Bartek Kozicki; Cees de Laat; Ana Lucia Varbanescu (DSD, 2020)

Designing and building application-centric parallel memories. - Giulio Stramondo; Catalin Bogdan Ciobanu; Cees de Laat; Ana Lucia Varbanescu (Concurr. Comput. Pract. Exp., 2020)