Design of a VLSI fuzzy processor for ATM traffic sources management. - Giuseppe Ascia; Giuseppe Ficili; Daniela Panno (LCN, 1995)

Design of a VLSI parallel processor for fuzzy computing. - Giuseppe Ascia; Vincenzo Catania (VLSI Design, 1995)

A VLSI Parallel Architecture for Fuzzy Expert Systems. - Vincenzo Catania; Giuseppe Ascia (Int. J. Pattern Recognit. Artif. Intell., 1995)

Designing for parallel fuzzy computing. - Giuseppe Ascia; Vincenzo Catania; Biagio Giacalone; Marco Russo; Lorenzo Vita (IEEE Micro, 1995)

Fuzzy Hardware Challenges. - Abraham Kandel; Giuseppe Ascia; Vincenzo Catania; Biagio Giacalone; Marco Russo; Lorenzo Vita; Andrés Jaramillo-Botero; Yoichi Miyake; Hua Harry Li; Nowell Godfrey; Yuandong Ji; Shuwei Guo; et al. (IEEE Micro, 1995)

An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning. - Giuseppe Ascia; Vincenzo Catania (Int. J. Artif. Intell. Tools, 1996)

A Reconfigurable Parallel Architecture for a Fuzzy Processor. - Giuseppe Ascia; Vincenzo Catania; Antonio Puliafito; Lorenzo Vita (Inf. Sci., 1996)

Design of a VLSI Hardware PET Decoder. - Giuseppe Ascia; Vincenzo Catania; Giuseppe Ficili (VLSI Design, 1997)

A VLSI fuzzy expert system for real-time traffic control in ATM networks. - Giuseppe Ascia; Vincenzo Catania; Giuseppe Ficili; Sergio Palazzo; Daniela Panno (IEEE Trans. Fuzzy Syst., 1997)

A Framework for a Parallel Architecture Dedicated to Soft Computing. - Giuseppe Ascia; Vincenzo Catania (VLSI Design, 1998)

An Optimized Parallel RISC Processor for Fuzzy Computing. - Giuseppe Ascia; Vincenzo Catania (Applied Informatics, 1999)

VLSI hardware architecture for complex fuzzy systems. - Giuseppe Ascia; Vincenzo Catania; Marco Russo (IEEE Trans. Fuzzy Syst., 1999)

A pipeline parallel architecture for a fuzzy inference processor. - Giuseppe Ascia; Vincenzo Catania (FUZZ-IEEE, 2000)

Parameterised system design based on genetic algorithms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (CODES, 2001)

A General Purpose Processor Oriented Fuzzy Reasoning. - Giuseppe Ascia; Vincenzo Catania (FUZZ-IEEE, 2001)

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (VLSI-SOC, 2001)

A Fuzzy Buffer Management Scheme For ATM and IP Networks. - Giuseppe Ascia; Vincenzo Catania; Giuseppe Ficili; Daniela Panno (INFOCOM, 2001)

An adaptive fuzzy threshold scheme for high performance shared-memory switches. - Giuseppe Ascia; Vincenzo Catania; Daniela Panno (SAC, 2001)

An efficient fuzzy system for traffic management in high-speed packet-switched networks. - Giuseppe Ascia; Vincenzo Catania; Daniela Panno (Soft Comput., 2001)

An Instruction-Level Power Analysis Model with Data Dependency. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Sarta (VLSI Design, 2001)

An efficient buffer management policy based on an integrated Fuzzy-GA approach. - Giuseppe Ascia; Vincenzo Catania; Daniela Panno (INFOCOM, 2002)

A Framework for Design Space Exploration of Parameterized VLSI Systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (ASP-DAC/VLSI Design, 2002)

An evolutionary approach for reducing the switching activity in address buses. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Antonio Parlato (IEEE Congress on Evolutionary Computation, 2003)

EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ESTIMedia, 2003)

An evolutionary approach for reducing the energy in address buses. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Antonio Parlato (ISICT, 2003)

A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (PATMOS, 2003)

A Genetic Approach To Bus Encoding. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (VLSI-SOC, 2003)

Multi-objective mapping for mesh-based NoC architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (CODES+ISSS, 2004)

Multi-objective Optimization of a Parameterized VLIW Architecture. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (Evolvable Hardware, 2004)

A GA-based design space exploration framework for parameterized system-on-a-chip platforms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (IEEE Trans. Evol. Comput., 2004)

Exploring Design Space of VLIW Architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ASAP, 2005)

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ASP-DAC, 2005)

An evolutionary approach to network-on-chip mapping problem. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (Congress on Evolutionary Computation, 2005)

Hyperblock formation: a power/energy perspective for high performance VLIW architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ISCAS (4), 2005)

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

An evolutionary management scheme in high-performance packet switches. - Giuseppe Ascia; Vincenzo Catania; Daniela Panno (IEEE/ACM Trans. Netw., 2005)

A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (IEEE Congress on Evolutionary Computation, 2006)

Fuzzy decision making in embedded system design. - Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (CODES+ISSS, 2006)

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ESTIMedia, 2006)

An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (ICSAMOS, 2006)

A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (J. Univers. Comput. Sci., 2006)

An integrated fuzzy-GA approach for buffer management. - Giuseppe Ascia; Vincenzo Catania; Daniela Panno (IEEE Trans. Fuzzy Syst., 2006)

Efficient design space exploration for application specific systems-on-a-chip. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (J. Syst. Archit., 2007)

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (IEEE Trans. Computers, 2008)

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. - Maurizio Palesi; Fabrizio Fazzino; Giuseppe Ascia; Vincenzo Catania (DSD, 2009)

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (Appl. Soft Comput., 2011)

Data Encoding Schemes in Networks on Chip. - Maurizio Palesi; Giuseppe Ascia; Fabrizio Fazzino; Vincenzo Catania (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems. - Alessandro G. Di Nuovo; Giuseppe Ascia; Vincenzo Catania (PPSN (2), 2012)

An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. - Giuseppe Ascia; Maurizio Palesi; Vincenzo Catania (DSD, 2013)

Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (DSD, 2013)

Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. - Andrea Mineo; Marina Masi; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (HPCC/EUC, 2013)

NoC links energy reduction through link voltage scaling. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (ICSAMOS, 2013)

A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers. - Alessandro G. Di Nuovo; Giuseppe Ascia (J. Intell. Fuzzy Syst., 2013)

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (DATE, 2014)

A Closed Loop Control based Power Manager for WiNoC Architectures. - Mohd Shahrizal Rusli; Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania; Muhammad N. Marsono (MES, 2014)

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. - Andrea Mineo; Mohd Shahrizal Rusli; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania; Muhammad N. Marsono (DATE, 2015)

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. - Maurizio Palesi; Davide Patti; Giuseppe Ascia; Daniela Panno; Vincenzo Catania (J. Comput. Sci., 2015)

Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection. - Giuseppe Ascia; Vincenzo Catania; Raffaele Di Natale; Andrea Fornaia; Misael Mongiovì; Salvatore Monteleone; Giuseppe Pappalardo; Emiliano Tramontana (WETICE, 2016)

Exploiting antenna directivity in wireless NoC architectures. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (Microprocess. Microsystems, 2016)

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Partha Pratim Pande; Vincenzo Catania (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Approximate Wireless Networks-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (DCIS, 2018)

Improving energy consumption of NoC based architectures through approximate communication. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (MECO, 2018)

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (IoTSMS, 2019)

Analyzing networks-on-chip based deep neural networks. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (NOCS, 2019)

DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. - Habiba Lahdhiri; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Jordane Lorandel; Emmanuelle Bourdel; Vincenzo Catania (DSD, 2020)

Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. - Giuseppe Ascia; Vincenzo Catania; John Jose; Salvatore Monteleone; Maurizio Palesi; Davide Patti (IPDPS Workshops, 2020)

Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. - Giuseppe Ascia; Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (NOCS, 2020)

Exploiting Data Resilience in Wireless Network-on-chip Architectures. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose; Valerio Mario Salerno (ACM J. Emerg. Technol. Comput. Syst., 2020)

LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Vincenzo Catania (PerCom Workshops, 2021)

MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DATE, 2022)

Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Habiba Lahdhiri; Salvatore Monteleone; Giuseppe Ascia; Vincenzo Catania (IPDPS Workshops, 2022)

Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Habiba Lahdhiri; Giuseppe Ascia; Vincenzo Catania (MECO, 2022)

DNN Model Compression for IoT Domain-Specific Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Andrea Mineo; Giuseppe Ascia; Vincenzo Catania (IEEE Internet Things J., 2022)

Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. - Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia; Davide Patti; Salvatore Monteleone; Vincenzo Catania (CF, 2023)

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. - Fabrizio Ferrandi; Serena Curzel; Leandro Fiorin; Daniele Ielmini; Cristina Silvano; Francesco Conti 001; Alessio Burrello; Francesco Barchi; Luca Benini; Luciano Lavagno; Teodoro Urso; Enrico Calore; et al. (CoRR, 2023)

Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Salvatore Monteleone; Giuseppe Ascia; Vincenzo Catania (IEEE Internet Things J., 2023)

A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. - Francesco Giulio Blanco; Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DAC, 2024)

Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. - Enrico Russo 002; Francesco Giulio Blanco; Maurizio Palesi; Giuseppe Ascia; Davide Patti; Vincenzo Catania (ISCAS, 2024)

Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures. - Maurizio Palesi; Enrico Russo 002; Davide Patti; Giuseppe Ascia; Vincenzo Catania (MCSoC, 2024)

Data-Driven Simulation Based Fault Detection in Automotive RISC-V Applications. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia (MCSoC, 2024)

Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia; Hamaad Rafique (MOST, 2024)

DNN Hardware Accelerator Selection for Feasible Deployment of MARL-Based MAC Protocols in Industrial IoT Networks. - Enrico Russo 002; Elio Vinciguerra; Giuseppe Ascia; Daniela Panno (RTSI, 2024)

Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (CoRR, 2024)

Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DATE, 2025)

An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia (PDP, 2025)

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. - Cristina Silvano; Daniele Ielmini; Fabrizio Ferrandi; Leandro Fiorin; Serena Curzel; Luca Benini; Francesco Conti 001; Angelo Garofalo; Cristian Zambelli; Enrico Calore; Sebastiano Fabio Schifano; Maurizio Palesi; et al. (ACM Comput. Surv., 2025)