A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops. - Giuseppe Natale; Giulio Stramondo; Pietro Bressana; Riccardo Cattaneo; Donatella Sciuto; Marco D. Santambrogio (ICCAD, 2016)

On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach. - Riccardo Cattaneo; Giuseppe Natale; Carlo Sicignano; Donatella Sciuto; Marco Domenico Santambrogio (ACM Trans. Archit. Code Optim., 2016)

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project. - Marco Rabozzi; Giuseppe Natale; Emanuele Del Sozzo; Alberto Scolari; Luca Stornaiuolo; Marco D. Santambrogio (DATE, 2017)

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains. - Alessandro Pappalardo; Giuseppe Natale; Marco Domenico Santambrogio (DSD, 2017)

Optimizing streaming stencil time-step designs via FPGA floorplanning. - Marco Rabozzi; Giuseppe Natale; Biagio Festa; Antonio Miele; Marco D. Santambrogio (FPL, 2017)

A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA. - Marco Bacis; Giuseppe Natale; Emanuele Del Sozzo; Marco Domenico Santambrogio (IPDPS Workshops, 2017)

On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks. - Giuseppe Natale; Marco Bacis; Marco Domenico Santambrogio (ISVLSI, 2017)

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project. - Marco Rabozzi; Rolando Brondolin; Giuseppe Natale; Emanuele Del Sozzo; Michael Hübner 001; Andreas Brokalakis; Catalin Bogdan Ciobanu; Dirk Stroobandt; Marco Domenico Santambrogio (ISVLSI, 2017)

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices. - Niccolo Raspa; Giuseppe Natale; Marco Bacis; Marco D. Santambrogio (IPDPS Workshops, 2018)

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils. - Enrico Reggiani; Giuseppe Natale; Carlo Moroni; Marco D. Santambrogio (IPDPS Workshops, 2018)

On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks. - Giuseppe Natale (2019)

Enabling transparent hardware acceleration on Zynq SoC for scientific computing. - Luca Stornaiuolo; Filippo Carloni; Riccardo Pressiani; Giuseppe Natale; Marco D. Santambrogio; Donatella Sciuto (SIGBED Rev., 2020)

Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components. - Enrico Reggiani; Emanuele Del Sozzo; Davide Conficconi; Giuseppe Natale; Carlo Moroni; Marco D. Santambrogio (ACM Trans. Reconfigurable Technol. Syst., 2021)

On the Computation of 2-Dimensional Recurrence Equations. - Giuseppe Natale (CoRR, 2024)