MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. - Alessio Franceschelli; Paolo Burgio; Giuseppe Tagliavini; Andrea Marongiu; Martino Ruggiero; Michele Lombardi 001; Alessio Bonfietti; Michela Milano; Luca Benini (Conf. Computing Frontiers, 2011)

Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. - Paolo Burgio; Giuseppe Tagliavini; Andrea Marongiu; Luca Benini (DATE, 2013)

Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. - Andrea Marongiu; Alessandro Capotondi; Giuseppe Tagliavini; Luca Benini (MES, 2013)

Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform. - Giuseppe Tagliavini; Germain Haugou; Luca Benini (Conf. Computing Frontiers, 2014)

Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators. - Giuseppe Tagliavini; Germain Haugou; Luca Benini (DASIP, 2014)

Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. - Paolo Burgio; Giuseppe Tagliavini; Francesco Conti 001; Andrea Marongiu; Luca Benini (DATE, 2014)

PULP: A parallel ultra low power platform for next generation IoT applications. - Davide Rossi; Francesco Conti 001; Andrea Marongiu; Antonio Pullini; Igor Loi; Michael Gautschi; Giuseppe Tagliavini; Alessandro Capotondi; Philippe Flatresse; Luca Benini (Hot Chips Symposium, 2015)

Exploring architectural heterogeneity in intelligent vision systems. - Nandhini Chandramoorthy; Giuseppe Tagliavini; Kevin M. Irick; Antonio Pullini; Siddharth Advani; Sulaiman Al Habsi; Matthew Cotter; John Sampson; Vijaykrishnan Narayanan; Luca Benini (HPCA, 2015)

Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. - Giuseppe Tagliavini; Davide Rossi; Luca Benini; Andrea Marongiu (ISVLSI, 2015)

ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators. - Giuseppe Tagliavini; Germain Haugou; Andrea Marongiu; Luca Benini (MCSoC, 2015)

A framework for optimizing OpenVX applications performance on embedded manycore accelerators. - Giuseppe Tagliavini; Germain Haugou; Andrea Marongiu; Luca Benini (SCOPES, 2015)

Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives. - Andrea Marongiu; Alessandro Capotondi; Giuseppe Tagliavini; Luca Benini (IEEE Trans. Ind. Informatics, 2015)

Enabling OpenVX support in mW-scale parallel accelerators. - Giuseppe Tagliavini; Germain Haugou; Andrea Marongiu; Luca Benini (CASES, 2016)

Always-on motion detection with application-level error control on a near-threshold approximate computing platform. - Giuseppe Tagliavini; Andrea Marongiu; Davide Rossi; Luca Benini (ICECS, 2016)

Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms. - Giuseppe Tagliavini (2017)

The transprecision computing paradigm: Concept, design, and applications. - A. Cristiano I. Malossi; Michael Schaffner; Anca Molnos; Luca Gammaitoni; Giuseppe Tagliavini; Andrew P. J. Emerson; Andrés Tomás; Dimitrios S. Nikolopoulos; Eric Flamand; Norbert Wehn (DATE, 2018)

A transprecision floating-point platform for ultra-low power computing. - Giuseppe Tagliavini; Stefan Mach; Davide Rossi; Andrea Marongiu; Luca Benini (DATE, 2018)

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. - Stefan Mach; Davide Rossi; Giuseppe Tagliavini; Andrea Marongiu; Luca Benini (ISCAS, 2018)

Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators. - Giuseppe Tagliavini; Germain Haugou; Andrea Marongiu; Luca Benini (J. Real Time Image Process., 2018)

Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. - Giuseppe Tagliavini; Davide Rossi; Andrea Marongiu; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking. - Giuseppe Tagliavini; Daniele Cesarini; Andrea Marongiu (IEEE Trans. Parallel Distributed Syst., 2018)

Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. - Giuseppe Tagliavini; Stefan Mach; Davide Rossi; Andrea Marongiu; Luca Benini (DATE, 2019)

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Giuseppe Tagliavini; Luca Benini (IEEE J. Solid State Circuits, 2019)

BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity. - Victor Javier Kartsch; Giuseppe Tagliavini; Marco Guermandi; Simone Benatti; Davide Rossi; Luca Benini (IEEE Trans. Biomed. Circuits Syst., 2019)

Combining learning and optimization for transprecision computing. - Andrea Borghesi; Giuseppe Tagliavini; Michele Lombardi 001; Luca Benini; Michela Milano (CF, 2020)

Enabling mixed-precision quantized neural networks in extreme-edge devices. - Nazareno Bruschi; Angelo Garofalo; Francesco Conti 001; Giuseppe Tagliavini; Davide Rossi (CF, 2020)

XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Davide Rossi; Luca Benini (DATE, 2020)

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. - Rohit Prasad; Satyajit Das; Kevin J. M. Martin; Giuseppe Tagliavini; Philippe Coussy; Luca Benini; Davide Rossi (DATE, 2020)

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (ISVLSI, 2020)

A transprecision floating-point cluster for efficient near-sensor data analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (CoRR, 2020)

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (CoRR, 2020)

FlexFloat: A Software Library for Transprecision Computing. - Giuseppe Tagliavini; Andrea Marongiu; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. - Fabio Montagna; Giuseppe Tagliavini; Davide Rossi; Angelo Garofalo; Luca Benini (ARCS, 2021)

Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. - Thorir Mar Ingolfsson; Andrea Cossettini; Xiaying Wang; Enrico Tabanelli; Giuseppe Tagliavini; Philippe Ryvlin; Luca Benini; Simone Benatti (BioCAS, 2021)

Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. - Emanuele Parisi; Francesco Barchi; Andrea Bartolini; Giuseppe Tagliavini; Andrea Acquaviva (DATE, 2021)

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Angelo Garofalo; Gianmarco Ottavi; Alfio Di Mauro; Francesco Conti 001; Giuseppe Tagliavini; Luca Benini; Davide Rossi (ESSCIRC, 2021)

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. - Nazareno Bruschi; Germain Haugou; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (ICCD, 2021)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. - Matteo Perotti; Giuseppe Tagliavini; Stefan Mach; Luca Bertaccini; Luca Benini (SAMOS, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes. - Benedetta Mazzoni; Simone Benatti; Luca Benini; Giuseppe Tagliavini (IEEE Embed. Syst. Lett., 2021)

DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. - Alessio Burrello; Angelo Garofalo; Nazareno Bruschi; Giuseppe Tagliavini; Davide Rossi; Francesco Conti 001 (IEEE Trans. Computers, 2021)

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (IEEE Trans. Emerg. Top. Comput., 2021)

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. - Florian Glaser; Giuseppe Tagliavini; Davide Rossi; Germain Haugou; Qiuting Huang; Luca Benini (IEEE Trans. Parallel Distributed Syst., 2021)

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. - Nazareno Bruschi; Giuseppe Tagliavini; Francesco Conti 001; Sergi Abadal; Albert Cabellos-Aparicio; Eduard Alarcón; Geethan Karunaratne; Irem Boybat; Luca Benini; Davide Rossi (AICAS, 2022)

PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. - Davide Nadalini; Manuele Rusci; Giuseppe Tagliavini; Leonardo Ravaglia; Luca Benini; Francesco Conti 001 (SAMOS, 2022)

An Optimized Heart Rate Detection System Based on Low-Power Microcontroller Platforms for Biosignal Processing. - Benedetta Mazzoni; Giuseppe Tagliavini; Luca Benini; Simone Benatti (SYSINT, 2022)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. - Enrico Tabanelli; Giuseppe Tagliavini; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (IEEE Trans. Parallel Distributed Syst., 2022)

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. - Nazareno Bruschi; Giuseppe Tagliavini; Angelo Garofalo; Francesco Conti 001; Irem Boybat; Luca Benini; Davide Rossi (DATE, 2023)

TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. - Seyed Ahmad Mirsalari; Giuseppe Tagliavini; Davide Rossi; Luca Benini (DATE, 2023)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. - Luca Valente; Yvan Tortorella; Mattia Sinigaglia; Giuseppe Tagliavini; Alessandro Capotondi; Luca Benini; Davide Rossi (DATE, 2023)

RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). - Francesco Barchi; Giacomo Pasini; Emanuele Parisi; Giuseppe Tagliavini; Andrea Bartolini; Andrea Acquaviva (PARMA-DITAM, 2023)

Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. - Seyed Ahmad Mirsalari; Saba Yousefzadeh; Giuseppe Tagliavini; Dimitrios Stathis 001; Ahmed Hemani (ICECS, 2023)

ANGELS - Smart Steering Wheel for Driver Safety. - Andrea Amidei; Pierangelo Maria Rapa; Giuseppe Tagliavini; Roberto Rabbeni; Paolo Pavan; Simone Benatti (IWASI, 2023)

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (CoRR, 2023)

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Alfio Di Mauro; Luca Benini; Davide Rossi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors. - Enrico Tabanelli; Giuseppe Tagliavini; Luca Benini (ACM Trans. Embed. Comput. Syst., 2023)

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms. - Amirhossein Kiamarzi; Davide Rossi; Giuseppe Tagliavini (CF, 2024)

SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story. - Gabriele Magnani; Daniele Cattaneo 002; Lev Denisov; Giuseppe Tagliavini; Giovanni Agosta; Stefano Cherubin (CF, 2024)

Balancing Accuracy and Energy Efficiency on Ultra-Law-Power Platforms for ECG Analysis. - Benedetta Mazzoni; Luca Bompani; Mattia Orlandi; Simone Benatti; Giuseppe Tagliavini (COINS, 2024)

Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. - Francesco Conti 001; Angelo Garofalo; Davide Rossi; Giuseppe Tagliavini; Luca Benini (CoRR, 2024)

ZeroNER: Fueling Zero-Shot Named Entity Recognition via Entity Type Descriptions. - Alessio Cocchieri; Marcos Martínez Galindo; Giacomo Frisoni; Gianluca Moro; Claudio Sartori 001; Giuseppe Tagliavini (ACL (Findings), 2025)

"What do you call a dog that is incontrovertibly true? Dogma": Testing LLM Generalization through Humor. - Alessio Cocchieri; Luca Ragazzi; Paolo Italiani; Giuseppe Tagliavini; Gianluca Moro (ACL (1), 2025)

Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. - Fatma Jebali; Caaliph Andriamisaina; Mathieu Jan; Wolfgang Ecker; Florian Egert; Bernhard Fischer; Alessio Burrello; Daniele Jahier Pagliari; Sara Vinco; Giuseppe Tagliavini; Ingo Feldner; Andreas Mauderer; et al. (DATE, 2025)

Enabling Real-Time Streaming Temporal Convolution Network Inference on Ultra-Low-Power Microcontrollers. - Seyed Ahmad Mirsalari; Marco Fariselli; Léo Bijar; Francesco Paci; Luca Benini; Giuseppe Tagliavini (ISVLSI, 2025)

OpenBioNER: Lightweight Open-Domain Biomedical Named Entity Recognition Through Entity Type Description. - Alessio Cocchieri; Giacomo Frisoni; Marcos Martínez Galindo; Gianluca Moro; Giuseppe Tagliavini; Francesco Candoli (NAACL (Findings), 2025)

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. - Mattia Sinigaglia; Amirhossein Kiamarzi; Marco Bertuletti; Luigi Ghionda; Mattia Orlandi; Riccardo Tedeschi; Aurora Di Giampietro; Yvan Tortorella; Luca Bertaccini; Simone Benatti; Giuseppe Tagliavini; Luca Benini; et al. (CoRR, 2025)

Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device. - Amirhossein Kiamarzi; Amirhossein Moallemi; Federica Zonzini; Davide Brunelli; Davide Rossi; Giuseppe Tagliavini (IEEE Internet Things J., 2025)

Synergistic Memory Optimisations: Precision Tuning in Heterogeneous Memory Hierarchies. - Gabriele Magnani; Daniele Cattaneo 002; Lev Denisov; Giuseppe Tagliavini; Giovanni Agosta; Stefano Cherubin (IEEE Trans. Computers, 2025)