13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction. - Yangho Seo; Jihee Choi; Sunki Cho; Hyunwook Han; Wonjong Kim; Gyeongha Ryu; Jungil Ahn; Younga Cho; Sungphil Choi; Seohee Lee; Wooju Lee; Chaehyuk Lee; et al. (ISSCC, 2024)