Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA. - Gnanasekaran Dhanabalan; Sankar Tamil Selvi (Comput. Stand. Interfaces, 2015)

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA. - Gnanasekaran Dhanabalan; Sankar Tamil Selvi; Miroslav Mahdal (Sensors, 2022)

Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW. - Gnanasekaran Dhanabalan; S. Tamil Selvi (Wirel. Pers. Commun., 2023)