A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. - Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake; Zhangcai Huang; Yasuaki Inoue (ISCAS, 2012)

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. - Qing Dong 002; Bo Yang 004; Gong Chen 002; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. - Gong Chen 002; Bo Yang 004; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2013)

A comparator energy model considering shallow trench isolation stress by geometric programming. - Gong Chen 002; Yu Zhang; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISQED, 2013)

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. - Yu Zhang; Gong Chen 002; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (VLSI-SoC, 2013)

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. - Yu Zhang; Gong Chen 002; Bo Yang 004; Jing Li 072; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. - Gong Chen 002; Yu Zhang; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Twin-row-style for MOS analog layout. - Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004; Gong Chen 002 (ICECS, 2016)

Routability of twisted common-centroid capacitor array under signal coupling constraints. - Gong Chen 002; Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004 (MWSCAS, 2016)

A multi-functional memory unit with PLA-based reconfigurable decoder. - Nobuyuki Yahiro; Bo Liu 031; Atsushi Nanri; Shigetoshi Nakatake; Yasuhiro Takashima; Gong Chen 002 (ReConFig, 2016)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. - Gong Chen 002; Toru Fujimura; Qing Dong 002; Shigetoshi Nakatake; Bo Yang 004 (ACM Trans. Design Autom. Electr. Syst., 2016)

Routable and Matched Layout Styles for Analog Module Generation. - Bo Liu 031; Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake (ACM Trans. Design Autom. Electr. Syst., 2018)