Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. - Tun Li; Yang Guo 003; Sikun Li; GongJie Liu (ATVA, 2005)

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. - Tun Li; Yang Guo 003; GongJie Liu; Sikun Li (DSD, 2005)

MA2TG: A Functional Test Program Generator for Microprocessor Verification. - Tun Li; Dan Zhu; Yang Guo 003; GongJie Liu; Sikun Li (DSD, 2005)