Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. - Gopalakrishnan Lakshminarayanan; B. Venkataramani (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Automation techniques for implementation of hybrid wave-pipelined 2D DWT. - G. Seetharaman; B. Venkataramani; Gopalakrishnan Lakshminarayanan (J. Real Time Image Process., 2008)

VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. - Gopalakrishnan Seetharaman; Balasubramanian Venkataramani; Gopalakrishnan Lakshminarayanan (VLSI Design, 2008)

Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio. - C. Vennila; Kumar Palaniappan CT; Kodati Vamsi Krishna; G. Lakshminarayanan; Seok-Bum Ko (ISCAS, 2012)

High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers. - K. Swaminathan; G. Lakshminarayanan; Seok-Bum Ko (ISED, 2012)

A Novel Encoding Scheme for Low Power in Network on Chip Links. - Deepa N. Sarma; Gopalakrishnan Lakshminarayanan; K. V. R. Suryakiran Chavali (VLSI Design, 2012)

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems. - C. Vennila; G. Lakshminarayanan; Seok-Bum Ko (Circuits Syst. Signal Process., 2012)

Design of a low power network interface for Network on chip. - K. Swaminathan; G. Lakshminarayanan; Frank Lang; Maher Fahmi; Seok-Bum Ko (CCECE, 2013)

Dynamic partial reconfigurable adaptive transceiver for OFDM based cognitive radio. - C. Vennila; K. Suresh 002; Rohit Rather; G. Lakshminarayanan; Seok-Bum Ko (CCECE, 2013)

Dynamic partial reconfigurable Viterbi decoder for wireless standards. - C. Vennila; Alok Kumar Patel; G. Lakshminarayanan; Seok-Bum Ko (Comput. Electr. Eng., 2013)

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip. - K. Swaminathan; G. Lakshminarayanan; Seok-Bum Ko (J. Low Power Electron., 2013)

QaMC - QoS Aware Multicast router for NoC fabric. - Sandeep Gopi Nambiar; K. Swaminathan; G. Lakshminarayanan; Seok-Bum Ko (CCECE, 2014)

A novel hybrid topology for Network on Chip. - K. Swaminathan; Sandeep Gopi Nambiar; Rajkumar; G. Lakshminarayanan; Seok-Bum Ko (CCECE, 2014)

Pipelined FFT architectures for real-time signal processing and wireless communication applications. - Antony Xavier Glittas; Gopalakrishnan Lakshminarayanan (VDAT, 2014)

Design and verification of an efficient WISHBONE-based network interface for network on chip. - K. Swaminathan; G. Lakshminarayanan; Seok-Bum Ko (Comput. Electr. Eng., 2014)

Low Power and Area Efficient Carry Select Adder. - Venkatachalam Nithish Kumar; Pani Prithvi Raj; Gopalakrishnan Lakshminarayanan; Mathini Sellathurai (J. Low Power Electron., 2014)

An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio. - Venkatachalam Nithish Kumar; Koteswara Rao Nalluri; Gopalakrishnan Lakshminarayanan; Mathini Sellathurai (J. Low Power Electron., 2015)

Two-parallel pipelined fast Fourier transform processors for real-valued signals. - Antony Xavier Glittas; Mathini Sellathurai; Gopalakrishnan Lakshminarayanan (IET Circuits Devices Syst., 2016)

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios. - Nithish Kumar Venkatachalam; Gopalakrishnan Lakshminarayanan; Mathini Sellathurai (IET Comput. Digit. Tech., 2016)

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. - Antony Xavier Glittas; Mathini Sellathurai; Gopalakrishnan Lakshminarayanan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design of Majority Logic Based Comparator. - Kartikeya Dubey; Marshal Raj; G. Lakshminarayanan (ICCCNT, 2018)

High Speed Controllable Inverter for Adder-Subtractor in QCA. - Marshal Raj; Raja Sekar Kumaresan; Gopalakrishnan Lakshminarayanan (ICCCNT, 2019)

Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique. - Marshal Raj; Raja Sekar Kumaresan; Gopalakrishnan Lakshminarayanan (ICCCNT, 2019)

A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption. - Aravindhan Alagarsamy; Gopalakrishnan Lakshminarayanan; Sundarakannan Mahilmaran; Seok-Bum Ko (IEEE Access, 2019)

KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC. - Aravindhan Alagarsamy; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (IET Comput. Digit. Tech., 2019)

Low-complex processing element architecture for successive cancellation decoder. - Geethu Sathees Babu; Lakshmi Renuka Madala; Gopalakrishnan Lakshminarayanan; Mathini Sellathurai (Integr., 2019)

Reconfigurable address generator for multi-standard interleaver. - Geethu Sathees Babu; Gopalakrishnan Lakshminarayanan (Microprocess. Microsystems, 2019)

Area-Efficient D-Flip Flop and XOR in QCA. - Raja Sekar Kumaresan; Marshal Raj; Gopalakrishnan Lakshminarayanan (ICCCNT, 2020)

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems. - Marshal Raj; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko; Nagi Naganathan; N. Ramasubramanian 001 (IEEE Embed. Syst. Lett., 2020)

High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block. - J. Sujanth Roy; G. Lakshminarayanan; Seok-Bum Ko (IEEE Embed. Syst. Lett., 2021)

Kinematic adaptive frequency sampling combined spatio temporal features for snow monitoring in aerospace applications. - Parameshwaran Ramalingam; Gopalakrishnan Lakshminarayanan; Manikandan Ramachandran; Rizwan Patan (Expert Syst. Appl., 2021)

Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology. - Marshal Raj; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (IET Comput. Digit. Tech., 2021)

A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition. - Bibin Sam Paul S; Antony Xavier Glittas; Gopalakrishnan Lakshminarayanan (Integr., 2021)

A novel boundary elemental analysis based frequency domain adaptive sampling technique for aerospace application. - R. Umamaheswaran; Parameshwaran Ramalingam; Marshal Raj; Gopalakrishnan Lakshminarayanan; S. Thiruppathirajan (Microprocess. Microsystems, 2021)

A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks. - Mohammadreza Asadikouhanjani; Hao Zhang 041; Gopalakrishnan Lakshminarayanan; Hyuk-Jae Lee; Seok-Bum Ko (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs. - Anantharaj Thalaimalai Vanaraj; Raja Sekar Kumaresan; Marshal Raj; G. Lakshminarayanan (ICCCNT, 2022)

Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs. - Anantharaj Thalaimalai Vanaraj; Raja Sekar Kumaresan; Marshal Raj; Anand Venkitachalam; G. Lakshminarayanan (ICCCNT, 2022)

Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata. - Marshal Raj; Raja Sekar Kumaresan; G. Lakshminarayanan (IEEE Des. Test, 2022)

High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata. - Raja Sekar Kumaresan; Marshal Raj; G. Lakshminarayanan (IEEE Embed. Syst. Lett., 2022)

FRDS: An efficient unique on-Chip interconnection network architecture. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (Integr., 2022)

An Efficient Lossless Telemetry Data Compression and Fault Analysis System Using 2SMLZ and CMOW-DLNN. - Parameshwaran Ramalingam; R. Thanuja; R. Bhavani 004; Gopalakrishnan Lakshminarayanan (Wirel. Pers. Commun., 2022)

Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem. - Utkarsh Tiwari; Satyanarayana Vollala; Natarajan Ramasubramanian; B. Shameedha Begum; G. Lakshminarayanan (J. Commun. Inf. Networks, 2022)

SMA: A constructive partitioning based mapping approach for Networks-on-Chip. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (Microprocess. Microsystems, 2022)

SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (J. Supercomput., 2023)

Framework for QCA Layout Generation and Rules for Rotated Cell Design. - Raja Sekar Kumaresan; Marshal Raj; Gopalakrishnan Lakshminarayanan (J. Circuits Syst. Comput., 2023)

Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators. - Muhammed Raees P. C; Akshayraj M. R; Varun P. Gopi; G. Lakshminarayanan; G. R. Gangadharan; Jayaraj U. Kidav (VDAT, 2024)

Energy-Efficient Hardware Design for CNN-Based ECG Signal Classification in Wearable Bio-Medical Devices. - Akshayraj M. R; Muhammed Raees P. C; Varun P. Gopi; G. Lakshminarayanan; G. R. Gangadharan; Jayaraj U. Kidav (VDAT, 2024)

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile. - T. S. Manivannan; K. R. Pasupathy; G. Lakshminarayanan (Microelectron. J., 2024)

Optimization of DE-QG TFET using novel CIP and DCT techniques. - T. S. Manivannan; K. R. Pasupathy; Mohd Rizwan Uddin Shaikh; G. Lakshminarayanan (Microelectron. J., 2024)