ALI: A procedural language to describe VLSI layouts. - Richard J. Lipton; Stephen C. North; Robert Sedgewick; Jacobo Valdes; Gopalakrishnan Vijayan (DAC, 1982)

VLSI Layout as Programming. - Richard J. Lipton; Jacobo Valdes; Gopalakrishnan Vijayan; Stephen C. North; Robert Sedgewick (ACM Trans. Program. Lang. Syst., 1983)

Worst case analysis of a graph coloring algorithm. - Jeremy P. Spinrad; Gopalakrishnan Vijayan (Discret. Appl. Math., 1985)

Rectilinear Graphs and their Embeddings. - Gopalakrishnan Vijayan; Avi Wigderson (SIAM J. Comput., 1985)

Geometry of Planar Graphs with Angles. - Gopalakrishnan Vijayan (SCG, 1986)

An improved edge bound on the interval number of a graph. - Jeremy P. Spinrad; Gopalakrishnan Vijayan; Douglas B. West (J. Graph Theory, 1987)

Optimal Node Ranking of Trees. - Ananth V. Iyer; H. Donald Ratliff; Gopalakrishnan Vijayan (Inf. Process. Lett., 1988)

A New Approach to the Rectilinear Steiner Tree Problem. - Jan-Ming Ho; Gopalakrishnan Vijayan; C. K. Wong (DAC, 1989)

Min-cost Partitioning on a Tree Structure and Applications. - Gopalakrishnan Vijayan (DAC, 1989)

Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree. - Jan-Ming Ho; Gopalakrishnan Vijayan; Chak-Kuen Wong (ICCAD, 1989)

On VHV-routing in channels with irregular boundaries. - Gopalakrishnan Vijayan; Hai Hsia Chen; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Floorplanning by Topological Constraint Reduction. - Gopalakrishnan Vijayan; Ren-Song Tsay (ICCAD, 1990)

Pad minimization for planar routing of multiple power nets. - Jan-Ming Ho; Majid Sarrafzadeh; Gopalakrishnan Vijayan; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Layer assignment for multichip modules. - Jan-Ming Ho; Majid Sarrafzadeh; Gopalakrishnan Vijayan; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

New algorithms for the rectilinear Steiner tree problem. - Jan-Ming Ho; Gopalakrishnan Vijayan; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Partitioning logic on graph structures to minimize routing cost. - Gopalakrishnan Vijayan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Test Application Timing: The Unexplored Issue in AC Test. - Vijay S. Iyengar; Gopalakrishnan Vijayan (ITC, 1991)

On an edge ranking problem of trees and graphs. - Ananth V. Iyer; H. Donald Ratliff; Gopalakrishnan Vijayan (Discret. Appl. Math., 1991)

Planar topological routing of pad nets. - Jan-Ming Ho; Gopalakrishnan Vijayan; C. K. Wong (Integr., 1991)

Generalization of Min-Cut Partitioning to Tree Structures and Its Applications. - Gopalakrishnan Vijayan (IEEE Trans. Computers, 1991)

A new method for floor planning using topological constraint reduction. - Gopalakrishnan Vijayan; Ren-Song Tsay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Workload-Driven Floorplanning for MIPS Optimization. - Pradip Bose; David LaPotin; Gopalakrishnan Vijayan; Sungho Kim (ICCD, 1992)

Optimized test application timing for AC test. - Vijay S. Iyengar; Gopalakrishnan Vijayan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

PEPPER - a timing driven early floorplanner. - Vinod Narayananan; David LaPotin; Rajesh Gupta 003; Gopalakrishnan Vijayan (ICCD, 1995)

Fast power loss calculation for digital static CMOS circuits. - Sergey Gavrilov; Alexey Glebov; Sergey G. Rusakov; David T. Blaauw; Larry G. Jones; Gopalakrishnan Vijayan (ED&TC, 1997)

Library-less synthesis for static CMOS combinational logic circuits. - Sergey Gavrilov; Alexey Glebov; Satyamurthy Pullela; S. C. Moore; Abhijit Dharchoudhury; Rajendran Panda; Gopalakrishnan Vijayan; David T. Blaauw (ICCAD, 1997)