A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. - Anant S. Kamath; Biman Chattopadhyay; Gopalkrishna Nayak (CICC, 2009)

A 1.8GHz Digital PLL in 65nm CMOS. - Biman Chattopadhyay; Anant S. Kamath; Gopalkrishna Nayak (VLSI Design, 2011)

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. - Krishnaswamy Nagaraj; Anant S. Kamath; Karthik Subburaj; Biman Chattopadhyay; Gopalkrishna Nayak; Satyasai Evani; Neeraj P. Nayak; Indu Prathapan; Frank Zhang; Baher Haroun (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. - Jayesh Wadekar; Biman Chattopadhyay; Ravi Mehta; Gopalkrishna Nayak (VLSID, 2016)

A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. - Biman Chattopadhyay; Sharath N. Bhat; Gopalkrishna Nayak; Ravi Mehta (VLSID, 2018)