Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. - Himanshu Thapliyal; Neela Gopi; K. K. Pavan Kumar; M. B. Srinivas (AICCSA, 2006)

Challenges in 3DIC implementation of a design using current CAD tools. - Gopi Neela; Jeffrey Draper (MWSCAS, 2012)

Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC. - Neela Gopi; Jeffrey Draper (3DIC, 2013)

An asymmetric adaptive-precision energy-efficient 3DIC multiplier. - Neela Gopi; Jeffrey Draper (ACM Great Lakes Symposium on VLSI, 2013)

Logic-on-logic partitioning techniques for 3-dimensional integrated circuits. - Neela Gopi; Jeffrey Draper (ISCAS, 2013)

Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC. - Neela Gopi; Jeffrey Draper (ISCAS, 2014)

Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach. - Neela Gopi; Jeffrey Draper (ISVLSI, 2014)

A multi-mode energy-efficient double-precision floating-point multiplier. - Gopi Neela; Jeffrey Draper (MWSCAS, 2014)

Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC. - Gopi Neela; Jeffrey Draper (3DIC, 2015)

Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. - Dipan Kumar Mandal; Srivatsava Jandhyala; Om Ji Omer; Gurpreet S. Kalsi; Biji George; Gopi Neela; Santhosh Kumar Rethinagiri; Sreenivas Subramoney; Lance Hacking; Jim Radford; Eagle Jones; Belliappa Kuttanna; et al. (DATE, 2019)