Hardware architecture of bi-cubic convolution interpolation for real-time image scaling. - Gopinath Mahale; Hamsika Mahale; Rajesh Babu Parimi; S. K. Nandy 001; S. Bhattacharya (FPT, 2014)

Hardware Solution for Real-Time Face Recognition. - Gopinath Mahale; Hamsika Mahale; Arnav Goel; S. K. Nandy 001; S. Bhattacharya; Ranjani Narayan (VLSID, 2015)

On the modeling of error functions as high dimensional landscapes for weight initialization in learning networks. - Julius; Gopinath Mahale; T. Sumana; C. S. Adityakrishna (SAMOS, 2016)

VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. - Gopinath Mahale; Soumitra Kumar Nandy; Eshan Bhatia; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. - Gopinath Mahale; Hamsika Mahale; S. K. Nandy 001; Ranjani Narayan (IEEE Trans. Parallel Distributed Syst., 2016)

OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. - Tobias Kenter; Gopinath Mahale; Samer Alhaddad; Yevgen Grynko; Christian Schmitt 003; Ayesha Afzal; Frank Hannig; Jens Förstner; Christian Plessl (FCCM, 2018)

Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (ISCAS, 2020)

IKW: Inter-Kernel Weights for Power Efficient Edge Computing. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Access, 2020)

WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices. - Gopinath Mahale; Pramod P. Udupa; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress. - Gopinath Mahale; Tejas Limbasiya; Muhammad Asad Aleem; Luis A. Plana; Aleksandar Duricic; Alireza Monemi; Xabier Abancens; Teresa Cervero; John D. Davis (ISC Workshops, 2023)