A System-on-Chip Implementation of the IEEE 802.11a MAC Layer. - Goran Panic; Daniel Dietterle; Zoran Stamenkovic; Klaus Tittelbach-Helmrich (DSD, 2003)

A System-On-Chip for Wireless Body Area Sensor Network Node. - Zoran Stamenkovic; Goran Panic; Günter Schoof (DDECS, 2008)

Architecture of a Power-Gated Wireless Sensor Node. - Goran Panic; Daniel Dietterle; Zoran Stamenkovic (DSD, 2008)

Power gating in wireless sensor networks. - Goran Panic; Zoran Stamenkovic; Rolf Kraemer (ISWPC, 2008)

An Encryption-Enabled Network Protocol Accelerator. - Steffen Peter; Mario Zessack; Frank Vater; Goran Panic; Horst Frankenfeldt; Michael Methfessel (WWIC, 2008)

Low power sensor node processor architecture. - Goran Panic; Thomas Basmer; Klaus Tittelbach-Helmrich; Lukasz Lopacinski (ICECS, 2010)

Performance evaluation of channel coding for Gbps 60-GHz OFDM-based wireless communications. - Miroslav Marinkovic; Maxim Piz; Chang-Soon Choi; Goran Panic; Marcus Ehrig; Eckhard Grass (PIMRC, 2010)

Sensor node processor for security applications. - Goran Panic; Thomas Basmer; Oliver Schrape; Steffen Peter; Frank Vater; Klaus Tittelbach-Helmrich (ICECS, 2011)

Performance Investigation on an MIMO-capable 802.11a Compliant MAC Protocol Implementation. - Emilija Miletic; Klaus Tittelbach-Helmrich; Goran Panic (MSN, 2011)

Fuzzy XML with Implementation. - Goran Panic; Milos Rackovic; Srdan Skrbic (BCI (Local), 2012)

The all IHP sensor node: highly integrated sensor nodes using IHP components. - Dan Kreiser; Marcin Brzozowski; Goran Panic; Sonom Olonbayar; Thomas Basmer; Peter Langendörfer (MOBIWAC, 2012)

Design of a sensor node crypto processor for IEEE 802.15.4 applications. - Goran Panic; Thomas Basmer; Schomann Henry; Steffen Peter; Frank Vater; Klaus Tittelbach-Helmrich (SoCC, 2012)

TNODE: A low power sensor node processor for secure wireless networks. - Goran Panic; Oliver Schrape; Thomas Basmer; Frank Vater; Klaus Tittelbach-Helmrich (ISSoC, 2013)

Fuzzy XML and prioritized fuzzy XQuery with implementation. - Goran Panic; Milos Rackovic; Srdan Skrbic (J. Intell. Fuzzy Syst., 2014)

Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design. - Goran Panic; Zoran Stamenkovic (DDECS, 2015)

Low Power Design Techniques. - Goran Panic (GI-Jahrestagung, 2015)

Möglichkeiten der Nutzung von RRAM in Low-Power Microcontrollern. - Frank Vater; Goran Panic; Mario Schölzel (GI-Jahrestagung, 2015)

An Embedded Sensor Node Microcontroller with Crypto-Processors. - Goran Panic; Oliver Stecklina; Zoran Stamenkovic (Sensors, 2016)

Low-Complexity Framework for Movement Classification Using Body-Worn Sensors. - Dwaipayan Biswas; Koushik Maharatna; Goran Panic; Evangelos B. Mazomenos; Josy Achner; Jasmin Klemke; Michael Jöbges; Steffen Ortmann (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Implementation of a Multi-Core Data Link Layer Processor for THz Communication. - Lukasz Lopacinski; Mohamed Hussein Eissa; Goran Panic; Marcin Brzozowski; Alireza Hasani; Rolf Kraemer (VTC Spring, 2018)

Modular Data Link Layer Processing for THz communication. - Lukasz Lopacinski; Mohamed Hussein Eissa; Goran Panic; Alireza Hasani; Rolf Kraemer (DDECS, 2019)

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology. - Lukasz Lopacinski; Miroslav Marinkovic; Goran Panic; Mohamed Hussein Eissa; Alireza Hasani; Karthik KrishneGowda; Rolf Kraemer (IEEE Access, 2019)

Classification of Space Particle Events using Supervised Machine Learning Algorithms. - Rijad Saric; Junchao Chen 001; Milos Krstic; Edhem Custovic; Goran Panic; Jasmin Kevric; Dejan Jokic (DSAA, 2021)

550 Gbps Fully Parallel Fully Unrolled LDPC Decoder in 28 nm CMOS Technology. - Alireza Hasani; Lukasz Lopacinski; Goran Panic; Eckhard Grass (EuCNC, 2022)

Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Oliver Schrape; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass (EuCNC, 2022)

On the SCA Resistance of Crypto IP Cores. - Zoya Dyka; Ievgen Kabin; Marcin Brzozowski; Goran Panic; Cristiano Calligaro; Milos Krstic; Peter Langendoerfer (LATS, 2022)

A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass; Rolf Kraemer (PIMRC, 2022)

High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass (VLSI-SoC, 2022)

Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Oliver Schrape; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass; Rolf Kraemer (VTC Spring, 2022)

High-Throughput Multi-Frame Decoding of QC-LDPC Codes With Modified Rejection-Based Minimum Finding. - Alireza Hasani; Lukasz Lopacinski; Goran Panic; Rolf Kraemer (IEEE Access, 2022)

Real-Valued Spreading Sequences for PSSS Based High-Speed Wireless Systems. - Lukasz Lopacinski; Nebojsa Maletic; Goran Panic; Alireza Hasani; Jesús Gutiérrez 004; Eckhard Grass (IEEE Access, 2022)

Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP. - Tim Henkes; Steffen Reith; Marc Stöttinger; Norbert Herfurth; Goran Panic; Julian Wälde; Fabian Buschkowski; Pascal Sasdrich; Christoph Lüth; Milan Funck; Tuba Kiyan; Arnd Weber; et al. (DATE, 2024)

On the Influence of Cell Libraries and Other Parameters to SCA Resistance of Crypto IP Cores. - Zoya Dyka; Ievgen Kabin; Marcin Brzozowski; Goran Panic; Cristiano Calligaro; Milos Krstic; Peter Langendoerfer (MECO, 2024)

Latch Based Design for Fast Voltage Droop Response. - Shreyas Srinivas; Ian W. Jones; Goran Panic; Christoph Lenzen 001 (CoRR, 2025)