A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. - Howard L. Kalter; Charles H. Stapper; John E. Barth Jr.; John DiLorenzo; Charles E. Drake; John A. Fifield; Gordon A. Kelley; Scott C. Lewis; Willem B. van der Hoeven; James A. Yankosky (IEEE J. Solid State Circuits, 1990)