General addressing mechanisms for microprocessors. - Gordon B. Steven; Fleur L. Williams (Microprocess. Microsystems, 1988)

A novel effective address calculation mechanism for RISC microprocessors. - Gordon B. Steven (SIGARCH Comput. Archit. News, 1988)

HARP: A parallel pipelined RISC processor. - Gordon B. Steven; Sue M. Gray; R. G. Adams (Microprocess. Microsystems, 1989)

Utilising low level parallelism in general purpose code: the HARP project. - R. G. Adams; Sue M. Gray; Gordon B. Steven (Microprocessing and Microprogramming, 1990)

How useful are complex instructions? A case study using the M68000. - Fleur L. Williams; Gordon B. Steven (Microprocessing and Microprogramming, 1990)

Address and data register separation on the M68000 family. - Fleur L. Williams; Gordon B. Steven (SIGARCH Comput. Archit. News, 1990)

A parallel pipelined processor with conditional instruction execution. - Rod Adams; Gordon B. Steven (SIGARCH Comput. Archit. News, 1991)

Addressing mechanisms for VLIW and superscalar processors. - Fleur L. Steven; Rod Adams; Gordon B. Steven; L. Wang; D. J. Whale (Microprocess. Microprogramming, 1993)

ALU design and processor branch architecture. - Gordon B. Steven; Fleur L. Steven (Microprocess. Microprogramming, 1993)

Static instruction scheduling for the HARP multiple-instruction-issue architecture. - Sue M. Gray; Rod Adams; G. J. Green; Gordon B. Steven (Microprocess. Microsystems, 1993)

Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler. - Rod Adams; Sue M. Gray; Gordon B. Steven (PDP, 1994)

An explicitly declared delayed-branch mechanism for a superscalar architecture. - Roger Collins; Gordon B. Steven (Microprocess. Microprogramming, 1994)

Hades-towards the design of an asynchronous superscalar processor. - C. J. Elston; D. B. Christianson; Paul A. Findlay; Gordon B. Steven (ASYNC, 1995)

Instruction Scheduling for a Superscalar Architecture. - Roger Collins; Gordon B. Steven (EUROMICRO, 1996)

Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture. - Richard D. Potter; Gordon B. Steven (Euro-Par, Vol. II, 1996)

A superscalar architecture to exploit instruction level parallelism. - Gordon B. Steven; Bruce Christianson; Roger Collins; Richard D. Potter; Fleur L. Steven (Microprocess. Microsystems, 1997)

The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. - Daniel Tate; Gordon B. Steven; Paul A. Findlay (EUROMICRO, 1998)

The impact of cache organisation on the instruction issue rate of a superscalar processor. - Lucian N. Vintan; Cristian Armat; Gordon B. Steven (PDP, 1999)

Static Scheduling for Out-of-order Instruction Issue Processors. - Daniel Tate; Gordon B. Steven; Fleur L. Steven (ACAC, 2000)

Applying Caching to Two-Level Adaptive Branch Prediction. - Colin Egan; Gordon B. Steven; Won Shim; Lucian N. Vintan (DSD, 2001)

Dynamic Branch Prediction Using Neural Networks. - Gordon B. Steven; Rubén Anguera; Colin Egan; Fleur L. Steven; Lucian N. Vintan (DSD, 2001)

Adding static data dependence collapsing to a high-performance instruction scheduler. - Fleur L. Steven; Colin Egan; Richard D. Potter; Gordon B. Steven (J. Syst. Archit., 2001)

Cached Two-Level Adaptive Branch Predictors with Multiple Stages. - Colin Egan; Gordon B. Steven; Lucian N. Vintan (ARCS, 2002)

Two-level branch prediction using neural networks. - Colin Egan; Gordon B. Steven; Patrick Quick; Rubén Anguera; Fleur L. Steven; Lucian N. Vintan (J. Syst. Archit., 2003)