Scanning tunneling microscopy of quasi-one-dimensional charge-density wave materials - Gordon Gammie (1991)

Expediting ramp-to-volume production. - Hari Balachandran; Jason Parker; Gordon Gammie; John W. Olson; Craig Force; Kenneth M. Butler; Sri Jandhyala (ITC, 1999)

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. - Gordon Gammie; Alice Wang; Minh Chau; Sumanth Gururajarao; Robert Pitts; Fabien Jumel; Stacey Engel; Philippe Royannez; Rolf Lagerquist; Hugh Mair; Jeff Vaccani; Greg Baldwin; et al. (ISSCC, 2008)

Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage. - Rahul Rithe; Jie Gu 007; Alice Wang; Satyendra Datla; Gordon Gammie; Dennis Buss; Anantha P. Chandrakasan (DATE, 2010)

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. - Gordon Gammie; Alice Wang; Hugh Mair; Rolf Lagerquist; Minh Chau; Philippe Royannez; Sumanth Gururajarao; Uming Ko (Proc. IEEE, 2010)

A 28nm 0.6V low-power DSP for mobile applications. - Gordon Gammie; Nathan Ickes; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (ISSCC, 2011)

Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations. - Rahul Rithe; Sharon Chou; Jie Gu 007; Alice Wang; Satyendra Datla; Gordon Gammie; Dennis Buss; Anantha P. Chandrakasan (VLSI Design, 2011)

A 28 nm 0.6 V Low Power DSP for Mobile Applications. - Nathan Ickes; Gordon Gammie; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (IEEE J. Solid State Circuits, 2012)

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. - Rahul Rithe; Sharon Chou; Jie Gu 007; Alice Wang; Satyendra Datla; Gordon Gammie; Dennis Buss; Anantha P. Chandrakasan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. - Alice Wang; Tsung-Yao Lin; Shichin Ouyang; Wei-Hung Huang; Jidong Wang; Shu-Hsin Chang; Sheng-Ping Chen; Chun-Hsiung Hu; J. C. Tai; Koan-Sin Tan; Meng-Nan Tsou; Ming-Hsien Lee; et al. (ISSCC, 2014)

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. - Hugh Mair; Gordon Gammie; Alice Wang; Sumanth Gururajarao; Ichiro Lin; HsinChen Chen; Wuan Kuo; Anand Rajagopalan; Wei-Zheng Ge; Rolf Lagerquist; Syed Rahman; C. J. Chung; et al. (ISSCC, 2015)

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. - Hugh Mair; Gordon Gammie; Alice Wang; Rolf Lagerquist; C. J. Chung; Sumanth Gururajarao; Ping Kao; Anand Rajagopalan; Anirban Saha; Amit Jain; Ericbill Wang; Shichin Ouyang; et al. (ISSCC, 2016)

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. - Hugh Mair; Ericbill Wang; Alice Wang; Ping Kao; Yuwen Tsai; Sumanth Gururajarao; Rolf Lagerquist; Jin Son; Gordon Gammie; Gordon Lin; Achuta Thippana; Kent Li; et al. (ISSCC, 2017)

2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC. - Hugh Mair; Ericbill Wang; Ashish Nayak; Rolf Lagerquist; Loda Chou; Gordon Gammie; HsinChen Chen; Lee-Kee Yong; Manzur Rahman; Jenny Wiedemeier; Ramu Madhavaram; Alex Chiou; et al. (ISSCC, 2020)

A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. - HsinChen Chen; Rolf Lagerquist; Ashish Nayak; Hugh Mair; Gokulakrishnan Manoharan; Ericbill Wang; Gordon Gammie; Efron Ho; Anand Rajagopalan; Lee-Kee Yong; Ramu Madhavaram; Madhur Jagota; et al. (ISSCC, 2021)

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. - Ashish Nayak; HsinChen Chen; Hugh Mair; Rolf Lagerquist; Tao Chen; Anand Rajagopalan; Gordon Gammie; Ramu Madhavaram; Madhur Jagota; C. J. Chung; Jenny Wiedemeier; Bala Meera; et al. (ISSCC, 2022)

2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC. - Anshul Varma; Sumanth Gururajarao; HsinChen Chen; Tao Chen; Gordon Gammie; Hugh Mair; Jen-Hang Yang; Hao-Hsiang Yu; Shun-Chieh Chang; Cheng-Hao Yang; Li-An Huang; Kumar Ramanathan; et al. (ISSCC, 2024)