Universal Schemes for Parallel Communication - Leslie G. Valiant; Gordon J. Brebner (STOC, 1981)

A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. - Gordon J. Brebner (Formal Aspects Comput., 1993)

Configurable array logic circuits for computing network error detection codes. - Gordon J. Brebner (J. VLSI Signal Process., 1993)

Use of Reconfigurability in Variable-Length Code Detection at Video Rates. - Gordon J. Brebner; John Gray (FPL, 1995)

A Virtual Hardware Operating System for the Xilinx XC6200. - Gordon J. Brebner (FPL, 1996)

The swappable logic unit: a paradigm for virtual hardware. - Gordon J. Brebner (FCCM, 1997)

Automatc identification of swappable logic units in XC6200 circuitry. - Gordon J. Brebner (FPL, 1997)

ECOLE: A Configurable Environment for a Local Optical Network of Workstations. - Gordon J. Brebner; Rob Pooley (CANPC, 1998)

Circlets: Circuits as Applets. - Gordon J. Brebner (FCCM, 1998)

Field-Programmable Logic: Catalyst for New Computing Paradigms. - Gordon J. Brebner (FPL, 1998)

An Interactive Datasheet for the Xilinx XC6200. - Gordon J. Brebner (FPL, 1998)

Runtime Reconfigurable Routing. - Gordon J. Brebner; Adam Donlin (IPPS/SPDP Workshops, 1998)

Reconfigurable Computing in Remote and Harsh Environments. - Gordon J. Brebner; Neil W. Bergmann (FPL, 1999)

A Transactional Approach to Configuring Telecommunications Services. - Tim Kempster; Gordon J. Brebner; Peter Thanisch (Databases in Telecommunications, 1999)

Circlets: Circuitry over the Internet. - Gordon J. Brebner; Irwin Kennedy (FCCM, 2001)

Chip-Based Reconfigurable Task Management. - Gordon J. Brebner; Oliver Diessel (FPL, 2001)

Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. - Gordon J. Brebner (FCCM, 2002)

Multithreading for Logic-Centric Systems. - Gordon J. Brebner (FPL, 2002)

Workshop Introduction. - Gordon J. Brebner (IPDPS, 2002)

Eccentric SoC Architectures as the Future Norm. - Gordon J. Brebner (DSD, 2003)

Software Decelerators. - Eric Keller; Gordon J. Brebner; Philip James-Roxby (FPL, 2003)

Networking on chip with platform FPGAs. - Gordon J. Brebner; Delon Levi (FPT, 2003)

Hyper-Programmable Architectures for Adaptable Networked Systems. - Gordon J. Brebner; Philip James-Roxby; Eric Keller; Chidamber Kulkarni (ASAP, 2004)

Mapping a domain specific language to a platform FPGA. - Chidamber Kulkarni; Gordon J. Brebner; Graham Schelle (DAC, 2004)

Time-Critical Software Deceleration in an FCCM. - Philip James-Roxby; Gordon J. Brebner; Dennis Bemmann (FCCM, 2004)

Programmable Logic Has More Computational Power than Fixed Logic. - Gordon J. Brebner (FPL, 2004)

Multithreading in a Hyper-programmable Platform for Networked Systems. - Philip James-Roxby; Gordon J. Brebner (FPL, 2004)

Programming a hyper-programmable architecture for networked systems. - Eric Keller; Gordon J. Brebner (FPT, 2004)

Mutable Codesign for Embedded Protocol Processing. - Todd S. Sproull; Gordon J. Brebner; Christopher E. Neely (FCCM, 2005)

06141 Executive Summary – Dynamically Reconfigurable Architectures. - Jürgen Becker 001; Jürgen Teich; Gordon J. Brebner; Peter M. Athanas (Dynamically Reconfigurable Architectures, 2006)

06141 Abstracts Collection – Dynamically Reconfigurable Architectures. - Jürgen Becker 001; Jürgen Teich; Gordon J. Brebner; Peter M. Athanas (Dynamically Reconfigurable Architectures, 2006)

Memory centric thread synchronization on platform FPGAs. - Chidamber Kulkarni; Gordon J. Brebner (DATE, 2006)

Systematic Characterization of Programmable Packet Processing Pipelines. - Michael Attig; Gordon J. Brebner (FCCM, 2006)

Building a flexible and scalable DRAM interface for networking applications on FPGAs. - Jike Chong; Chidamber Kulkarni; Gordon J. Brebner (FPGA, 2006)

Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. - Chidamber Kulkarni; Gordon J. Brebner (FPL, 2006)

Editorial for the Special Issue on Field Programmable Technology. - Gordon J. Brebner; Samarjit Chakraborty; Weng-Fai Wong (J. VLSI Signal Process., 2007)

OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. - Shuvra S. Bhattacharyya; Gordon J. Brebner; Jörn W. Janneck; Johan Eker; Carl von Platen; Marco Mattavelli; Mickaël Raulet (SIGARCH Comput. Archit. News, 2008)

Packets everywhere: The great opportunity for field programmable technology. - Gordon J. Brebner (FPT, 2009)

ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. - Christopher E. Neely; Gordon J. Brebner; Weijia Shang (FCCM, 2010)

Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. - Christopher E. Neely; Gordon J. Brebner; Weijia Shang (FPL, 2010)

400 Gb/s Programmable Packet Parsing on a Single FPGA. - Michael Attig; Gordon J. Brebner (ANCS, 2011)

Reconfigurable Computing for High Performance Networking Applications. - Gordon J. Brebner (ARC, 2011)

Softly defined networking. - Gordon J. Brebner (ANCS, 2012)

Optimizing packet lookup in time and space on FPGA. - Thilan Ganegedara; Viktor K. Prasanna; Gordon J. Brebner (FPL, 2012)

ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. - Christopher E. Neely; Gordon J. Brebner; Weijia Shang (ACM Trans. Reconfigurable Technol. Syst., 2013)

High-Speed Packet Processing using Reconfigurable Computing. - Gordon J. Brebner; Weirong Jiang (IEEE Micro, 2014)

Programmable hardware for software defined networks. - Gordon J. Brebner (ECOC, 2015)

Programmable hardware in software defined networking. - Gordon J. Brebner (OFC, 2015)

Programmable hardware for high performance SDN. - Gordon J. Brebner (OFC, 2015)

Whippersnapper: A P4 Language Benchmark Suite. - Huynh Tu Dang; Han Wang 009; Theo Jepsen; Gordon J. Brebner; Changhoon Kim; Jennifer Rexford; Robert Soulé; Hakim Weatherspoon (SOSR, 2017)

FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. - Guanwen Zhong; Haris Javaid; Hassaan Saadat; Lingchao Xu; Chengchen Hu; Gordon J. Brebner (CVCBT, 2019)

The P4->NetFPGA Workflow for Line-Rate Packet Processing. - Stephen Ibanez; Gordon J. Brebner; Nick McKeown; Noa Zilberman (FPGA, 2019)

Event-Driven Packet Processing. - Stephen Ibanez; Gianni Antichi; Gordon J. Brebner; Nick McKeown (HotNets, 2019)

Optimizing Validation Phase of Hyperledger Fabric. - Haris Javaid; Chengchen Hu; Gordon J. Brebner (MASCOTS, 2019)

Adaptable Switch: A Heterogeneous Switch Architecture for Network-Centric Computing. - Siyi Qiao; Chengchen Hu; Gordon J. Brebner; Jianhua Zou; Xiaohong Guan (IEEE Commun. Mag., 2020)

Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. - Haris Javaid; Ji Yang; Nathania Santoso; Mohit Upadhyay; Sundararajarao Mohan; Chengchen Hu; Gordon J. Brebner (ICDCS, 2022)