Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. - Gordon R. Chiu; Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (ICCAD, 2006)

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (SLIP, 2006)

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Very Large Scale Integr. Syst., 2007)

The Stratix™ 10 Highly Pipelined FPGA Architecture. - David M. Lewis; Gordon R. Chiu; Jeffrey Chromczak; David R. Galloway; Ben Gamsa; Valavan Manohararajah; Ian Milton; Tim Vanderhoek; John Van Dyken (FPGA, 2016)

An OpenCL™ Deep Learning Accelerator on Arria 10. - Utku Aydonat; Shane O'Connell; Davor Capalija; Andrew C. Ling; Gordon R. Chiu (FPGA, 2017)

Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. - Andrew C. Ling; Utku Aydonat; Shane O'Connell; Davor Capalija; Gordon R. Chiu (IWOCL, 2017)

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. - Mohamed S. Abdelfattah; David Han; Andrew Bitar; Roberto DiCecco; Shane O'Connell; Nitika Shanker; Joseph Chu; Ian Prins; Joshua Fender; Andrew C. Ling; Gordon R. Chiu (FPL, 2018)

Harnessing Numerical Flexibility for Deep Learning on FPGAs. - Andrew C. Ling; Mohamed S. Abdelfattah; Shane O'Connell; Andrew Bitar; David Han; Roberto DiCecco; Suchit Subhaschandra; Chris N. Johnson; Dmitry Denisenko; Joshua Fender; Gordon R. Chiu (HEART, 2018)

Flexibility: FPGAs and CAD in Deep Learning Acceleration. - Gordon R. Chiu; Andrew C. Ling; Davor Capalija; Andrew Bitar; Mohamed S. Abdelfattah (ISPD, 2018)