A Practical Online Design Rule Checking System. - Goro Suzuki; Yoshio Okamura (DAC, 1990)

MOSAIC: a tile-based datapath layout generator. - Goro Suzuki; Tetsuya Yamamoto; Kyoji Yuyama; Kotaro Hirasawa (ICCAD, 1992)

VLSI interconnect delay analysis method for ramp input signal. - Nobuyuki Mihara; Goro Suzuki (ASICON, 2011)

Separate projection and extended Cauer method for circuit reduction. - Goro Suzuki (ASICON, 2011)

Interconnect waveform calculation method with parameter variation. - Goro Suzuki; Ryo Yamanaka (ASICON, 2013)

Multiple terminal reduction method. - Goro Suzuki (SoCC, 2013)

Waveform base clock tree delay analysis using parallel processing. - Goro Suzuki (ASICON, 2015)