Minimizing the Number of Paths in BDDs. - Görschwin Fey; Rolf Drechsler (SBCCI, 2002)

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. - Junhao Shi; Görschwin Fey; Rolf Drechsler (Asian Test Symposium, 2003)

MuTaTe: an efficient design for testability technique for multiplexor based circuits. - Rolf Drechsler; Junhao Shi; Görschwin Fey (ACM Great Lakes Symposium on VLSI, 2003)

Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. - Görschwin Fey; Sebastian Kinder; Rolf Drechsler (ISMVL, 2003)

Modeling Multi-Valued Circuits in SystemC. - Daniel Große; Görschwin Fey; Rolf Drechsler (ISMVL, 2003)

Cost-efficient Formal Block Verification for ASIC Design. - Klaus Winkelmann; Hans-Joachim Trylus; Dominik Stoffel; Görschwin Fey (MBMV, 2003)

Finding Good Counter-Examples to Aid Design Verification. - Görschwin Fey; Rolf Drechsler (MEMOCODE, 2003)

Improving simulation-based verification by means of formal methods. - Görschwin Fey; Rolf Drechsler (ASP-DAC, 2004)

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. - Klaus Winkelmann; Hans-Joachim Trylus; Dominik Stoffel; Görschwin Fey (DATE, 2004)

BDD Circuit Optimization for Path Delay Fault Testability. - Görschwin Fey; Junhao Shi; Rolf Drechsler (DSD, 2004)

Disjoint Sum of Product Minimization by Evolutionary Algorithms. - Nicole Drechsler; Mario Hilgemeier; Görschwin Fey; Rolf Drechsler (EvoWorkshops, 2004)

Algorithms for Taylor Expansion Diagrams. - Görschwin Fey; Rolf Drechsler; Maciej J. Ciesielski (ISMVL, 2004)

Synthesis of fully testable circuits from BDDs. - Rolf Drechsler; Junhao Shi; Görschwin Fey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Advanced BDD optimization. - Rüdiger Ebendt; Görschwin Fey; Rolf Drechsler (Springer, 2005)

Bridging fault testability of BDD circuits. - Junhao Shi; Görschwin Fey; Rolf Drechsler (ASP-DAC, 2005)

Utilizing don't care states in SAT-based bounded sequential problems. - Sean Safarpour; Görschwin Fey; Andreas G. Veneris; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2005)

Controlling the Memory During Manipulation of Word-Level Decision Diagrams. - Sebastian Kinder; Görschwin Fey; Rolf Drechsler (ISMVL, 2005)

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. - Junhao Shi; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (ISVLSI, 2005)

SyCE: An Integrated Environment for System Design in SystemC. - Rolf Drechsler; Görschwin Fey; Christian Genz; Daniel Große (IEEE International Workshop on Rapid System Prototyping, 2005)

Increasing robustness and usability of circuit design tools by using formal techniques. - Görschwin Fey (2006)

Avoiding false negatives in formal verification for protocol-driven blocks. - Görschwin Fey; Daniel Große; Rolf Drechsler (DATE, 2006)

On the relation between simulation-based and SAT-based diagnosis. - Görschwin Fey; Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (DATE, 2006)

Increasing robustness and usability of circuit design tools by using formal techniques. - Görschwin Fey (Ausgezeichnete Informatikdissertationen, 2006)

Efficiency of Multi-Valued Encoding in SAT-based ATPG. - Görschwin Fey; Junhao Shi; Rolf Drechsler (ISMVL, 2006)

SAT-based Calculation of Source Code Coverage for BMC. - Görschwin Fey; Rolf Drechsler (MBMV, 2006)

Automatic Test Pattern Generation. - Rolf Drechsler; Görschwin Fey (SFM, 2006)

An Integrated Approach for Combining BDD and SAT Provers. - Rolf Drechsler; Görschwin Fey; Sebastian Kinder (VLSI Design, 2006)

Minimizing the number of paths in BDDs: Theory and algorithm. - Görschwin Fey; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Instance Generation for SAT-based ATPG. - Daniel Tille; Görschwin Fey; Rolf Drechsler (DDECS, 2007)

SAT-based ATPG for Path Delay Faults in Sequential Circuits. - Stephan Eggersglüß; Görschwin Fey; Rolf Drechsler (ISCAS, 2007)

Experimental Studies on SAT-Based ATPG for Gate Delay Faults. - Stephan Eggersglüß; Daniel Tille; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (ISMVL, 2007)

Formal Verification on the Word Level using SAT-like Proof Techniques. - Görschwin Fey; Daniel Große; Stephan Eggersglüß; Robert Wille; Rolf Drechsler (MBMV, 2007)

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. - André Sülflow; Görschwin Fey; Rolf Drechsler (MBMV, 2007)

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. - Stephan Eggersglüß; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (MEMOCODE, 2007)

SWORD: A SAT like Prover Using Word Level Information. - Robert Wille; Görschwin Fey; Daniel Große; Stephan Eggersglüß; Rolf Drechsler (VLSI-SoC (Selected Papers), 2007)

Reusing Learned Information in SAT-based ATPG. - Görschwin Fey; Tim Warode; Rolf Drechsler (VLSI Design, 2007)

Robustness and usability in modern design flows. - Görschwin Fey; Rolf Drechsler (Springer, 2008)

Targeting Leakage Constraints during ATPG. - Görschwin Fey; Satoshi Komatsu; Yasuo Furukawa; Masahiro Fujita (ATS, 2008)

SAT-based Automatic Test Pattern Generation. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Daniel Tille (Evolutionary Test Generation, 2008)

Automatic Generation of Complex Properties for Hardware Designs. - Frank Rogin; Thomas Klotz; Görschwin Fey; Rolf Drechsler; Steffen Rülke (DATE, 2008)

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. - Robert Wille; Görschwin Fey; Marc Messing; Gerhard Angst; Lothar Linhard; Rolf Drechsler (DSD, 2008)

Using unsatisfiable cores to debug multiple design errors. - André Sülflow; Görschwin Fey; Roderick Bloem; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2008)

A Basis for Formal Robustness Checking. - Görschwin Fey; Rolf Drechsler (ISQED, 2008)

Debugging Design Errors by Using Unsatisfiable Cores. - André Sülflow; Görschwin Fey; Roderick Bloem; Rolf Drechsler (MBMV, 2008)

On the construction of small fully testable circuits with low depth. - Görschwin Fey; Anna Bernasconi 001; Valentina Ciriani; Rolf Drechsler (Microprocess. Microsystems, 2008)

On Acceleration of SAT-Based ATPG for Industrial Designs. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Daniel Tille (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Automatic Fault Localization for Property Checking. - Görschwin Fey; Stefan Staber; Roderick Bloem; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Test Pattern Generation using Boolean Proof Engines. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Daniel Tille (Springer, 2009)

Deterministic Algorithms for ATPG under Leakage Constraints. - Görschwin Fey (Asian Test Symposium, 2009)

Computing bounds for fault tolerance using formal techniques. - Görschwin Fey; André Sülflow; Rolf Drechsler (DAC, 2009)

Robustness Check for Multiple Faults Using Formal Techniques. - Stefan Frehse; Görschwin Fey; André Sülflow; Rolf Drechsler (DSD, 2009)

SAT-based ATPG testing of inter- and intra-gate bridging faults. - Toru Nakura; Yutaro Tatemura; Görschwin Fey; Makoto Ikeda; Satoshi Komatsu; Kunihiro Asada (ECCTD, 2009)

Evaluation of Cardinality Constraints on SMT-Based Debugging. - André Sülflow; Robert Wille; Görschwin Fey; Rolf Drechsler (ISMVL, 2009)

Increasing the Accuracy of SAT-based Debugging. - André Sülflow; Görschwin Fey; Cécile Braunstein; Ulrich Kühne; Rolf Drechsler (MBMV, 2009)

WoLFram- A Word Level Framework for Formal Verification. - André Sülflow; Ulrich Kühne; Görschwin Fey; Daniel Große; Rolf Drechsler (IEEE International Workshop on Rapid System Prototyping, 2009)

Advanced verification by automatic property generation. - Frank Rogin; Thomas Klotz; Görschwin Fey; Rolf Drechsler; Steffen Rülke (IET Comput. Digit. Tech., 2009)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Jürgen Schlöffel; Daniel Tille (it Inf. Technol., 2009)

Formal verification meets robustness checking - Techniques and challenges. - Rolf Drechsler; Görschwin Fey (DDECS, 2010)

A better-than-worst-case robustness measure. - Stefan Frehse; Görschwin Fey; Rolf Drechsler (DDECS, 2010)

RobuCheck: a robustness checker for digital circuits. - Stefan Frehse; Görschwin Fey; André Sülflow; Rolf Drechsler (DYADEM-FTS@EDCC, 2010)

Evaluating Debugging Algorithms from a Qualitative Perspective. - Alexander Finder; Görschwin Fey (FDL, 2010)

Polynomial datapath optimization using constraint solving and formal modelling. - Finn Haedicke; Bijan Alizadeh; Görschwin Fey; Masahiro Fujita; Rolf Drechsler (ICCAD, 2010)

Using QBF to increase accuracy of SAT-based debugging. - André Sülflow; Görschwin Fey; Rolf Drechsler (ISCAS, 2010)

Towards Unifying Localization and Explanation for Automated Debugging. - Görschwin Fey; André Sülflow; Rolf Drechsler (MTV, 2010)

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. - Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Rolf Drechsler (J. Electron. Test., 2010)

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). - Görschwin Fey; André Sülflow; Stefan Frehse; Rolf Drechsler (it Inf. Technol., 2010)

Orchestrated multi-level information flow analysis to understand SoCs. - Görschwin Fey (DAC, 2011)

Automatic property generation for the formal verification of bus bridges. - Mathias Soeken; Ulrich Kühne; Martin Freibothe; Görschwin Fey; Rolf Drechsler (DDECS, 2011)

metaSMT: Focus on Your Application not on Solver Integration. - Finn Haedicke; Stefan Frehse; Görschwin Fey; Daniel Große; Rolf Drechsler (DIFTS@FMCAD, 2011)

Test Case Generation from Mutants Using Model Checking Techniques. - Heinz Riener; Roderick Bloem; Görschwin Fey (ICST Workshops, 2011)

Towards Automatic Property Generation for the Formal Verification of Bus Bridges. - Mathias Soeken; Ulrich Kühne; Martin Freibothe; Görschwin Fey; Rolf Drechsler (MBMV, 2011)

Assessing System Vulnerability Using Formal Verification Techniques. - Görschwin Fey (MEMICS, 2011)

Effective Robustness Analysis Using Bounded Model Checking Techniques. - Görschwin Fey; André Sülflow; Stefan Frehse; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Automated Post-Silicon Debugging of Failing Speedpaths. - Mehdi Dehbashi; Görschwin Fey (Asian Test Symposium, 2012)

Automated feature localization for hardware designs using coverage metrics. - Jan Malburg; Alexander Finder; Görschwin Fey (DAC, 2012)

Automated debugging from pre-silicon to post-silicon. - Mehdi Dehbashi; Görschwin Fey (DDECS, 2012)

On Modeling and Evaluation of Logic Circuits under Timing Variations. - Mehdi Dehbashi; Görschwin Fey; Kaushik Roy 001; Anand Raghunathan (DSD, 2012)

Functional analysis of circuits under timing variations. - Mehdi Dehbashi; Görschwin Fey; Kaushik Roy 001; Anand Raghunathan (ETS, 2012)

Complete and effective robustness checking by means of interpolation. - Stefan Frehse; Görschwin Fey; Eli Arbel; Karen Yorav; Rolf Drechsler (FMCAD, 2012)

FoREnSiC- An Automatic Debugging Environment for C Programs. - Roderick Bloem; Rolf Drechsler; Görschwin Fey; Alexander Finder; Georg Hofferek; Robert Könighofer; Jaan Raik; Urmas Repinski; André Sülflow (Haifa Verification Conference, 2012)

Model-based diagnosis versus error explanation. - Heinz Riener; Görschwin Fey (MEMOCODE, 2012)

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. - Heinz Riener; Görschwin Fey (SPIN, 2012)

Verifying Reliability (Dagstuhl Seminar 12341). - Görschwin Fey; Masahiro Fujita; Natasa Miskov-Zivanov; Kaushik Roy 001; Matteo Sonza Reorda (Dagstuhl Reports, 2012)

Reliability analysis reloaded: how will we survive? - Robert C. Aitken; Görschwin Fey; Zbigniew T. Kalbarczyk; Frank Reichenbach; Matteo Sonza Reorda (DATE, 2013)

Tuning dynamic data flow analysis to support design understanding. - Jan Malburg; Alexander Finder; Görschwin Fey (DATE, 2013)

Improving fault tolerance utilizing hardware-software-co-synthesis. - Heinz Riener; Stefan Frehse; Görschwin Fey (DATE, 2013)

Efficient automated speedpath debugging. - Mehdi Dehbashi; Görschwin Fey (DDECS, 2013)

Debugging HDL designs based on functional equivalences with high-level specifications. - Alexander Finder; Jan-Philipp Witte; Görschwin Fey (DDECS, 2013)

Yet a Better Error Explanation Algorithm (Extended Abstract). - Heinz Riener; Görschwin Fey (MBMV, 2013)

Debug Automation for Logic Circuits Under Timing Variations. - Mehdi Dehbashi; Görschwin Fey (IEEE Des. Test, 2013)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. - Daniel Große; Görschwin Fey; Rolf Drechsler (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013)

Automated design debugging in a testbench-based verification environment. - Mehdi Dehbashi; André Sülflow; Görschwin Fey (Microprocess. Microsystems, 2013)

Automatically connecting hardware blocks via light-weight matching techniques. - Jan Malburg; Niklas Krafczyk; Görschwin Fey (DDECS, 2014)

Sat-based speedpath debugging using waveforms. - Mehdi Dehbashi; Görschwin Fey (ETS, 2014)

MetaSMT: a unified interface to SMT-LIB2. - Heinz Riener; Mathias Soeken; Clemens Werther; Görschwin Fey; Rolf Drechsler (FDL, 2014)

SAT-based speedpath debugging using X traces. - Mehdi Dehbashi; Görschwin Fey (IDT, 2014)

A Logic for Cardinality Constraints (Extended Abstract). - Heinz Riener; Oliver Keszöcze; Rolf Drechsler; Görschwin Fey (MBMV, 2014)

Equivalence Checking on System Level using Stepwise Induction. - Niels Thole; Görschwin Fey (MBMV, 2014)

Mutation Based Feature Localization. - Jan Malburg; Emmanuelle Encrenaz-Tiphène; Görschwin Fey (MTV, 2014)

Debug Automation for Synchronization Bugs at RTL. - Mehdi Dehbashi; Görschwin Fey (VLSID, 2014)

Latency Analysis for Sequential Circuits. - Alexander Finder; André Sülflow; Görschwin Fey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Simulation-Based Approach for Automated Feature Localization. - Jan Malburg; Alexander Finder; Görschwin Fey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. - Tino Flenker; André Sülflow; Görschwin Fey (ATS, 2015)

Equivalence Checking on System Level Using a Priori Knowledge. - Niels Thole; Heinz Riener; Görschwin Fey (DDECS, 2015)

Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. - Gökçe Aydos; Görschwin Fey (GI-Jahrestagung, 2015)

Conservatively Analyzing Transient Faults. - Niels Thole; Görschwin Fey; Alberto García Ortiz (ISVLSI, 2015)

Execution Tracing of C Code for Formal Analysis (Extended Abstract). - Heinz Riener; Michael Kirkedal Thomsen; Görschwin Fey (MBMV, 2015)

In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR. - Gökçe Aydos; Görschwin Fey (SyDe Summer School, 2015)

Formal Verification of Robustness. - Niels Thole; Görschwin Fey (SyDe Summer School, 2015)

Path-Based Program Repair. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (FESCA, 2015)

Transaction-based online debug for NoC-based multiprocessor SoCs. - Mehdi Dehbashi; Görschwin Fey (Microprocess. Microsystems, 2015)

SMT-Based CPS Parameter Synthesis. - Heinz Riener; Robert Könighofer; Görschwin Fey; Roderick Bloem (ARCH@CPSWeek, 2016)

Exploiting error detection latency for parity-based soft error detection. - Gökçe Aydos; Görschwin Fey (DDECS, 2016)

A hybrid algorithm to conservatively check the robustness of circuits. - Niels Thole; Lorena Anghel; Görschwin Fey (ETS, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

Equivalence checking on ESL utilizing a priori knowledge. - Niels Thole; Heinz Riener; Görschwin Fey (FDL, 2016)

Multilevel design understanding: from specification to logic (invited paper). - Sandip Ray; Ian G. Harris; Görschwin Fey; Mathias Soeken (ICCAD, 2016)

Exact diagnosis using boolean satisfiability. - Heinz Riener; Görschwin Fey (ICCAD, 2016)

On the robustness of DCT-based compression algorithms for space applications. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey; Jan-Gerd Mess; Robert Schmidt 003 (IOLTS, 2016)

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. - Niels Thole; Görschwin Fey; Alberto García Ortiz (ISVLSI, 2016)

Counterexample-guided diagnosis. - Heinz Riener; Görschwin Fey (IVSW, 2016)

Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey (LATS, 2016)

Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern. - Pascal Pieper; Fabian Greif; Görschwin Fey (Echtzeit, 2016)

WCET overapproximation for software in the context of a Cyber-Physical System. - Niklas Krafczyk; Heinz Riener; Görschwin Fey (VLSI-SoC, 2016)

Debugging hardware designs using dynamic dependency graphs. - Jan Malburg; Alexander Finder; Görschwin Fey (Microprocess. Microsystems, 2016)

Property mining using dynamic dependency graphs. - Jan Malburg; Tino Flenker; Görschwin Fey (ASP-DAC, 2017)

CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (ASP-DAC, 2017)

Mapping abstract and concrete hardware models for design understanding. - Tino Flenker; Görschwin Fey (DDECS, 2017)

Temporal redundancy latch-based architecture for soft error mitigation. - Robert Schmidt 003; Alberto García Ortiz; Görschwin Fey (IOLTS, 2017)

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. - Tino Flenker; Jan Malburg; Görschwin Fey; Serhiy Avramenko; Massimo Violante; Matteo Sonza Reorda (ISVLSI, 2017)

Counterexample-Guided EF Synthesis of Boolean Functions. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (MBMV, 2017)

A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey (J. Electron. Test., 2017)

Empirical results on parity-based soft error detection with software-based retry. - Gökçe Aydos; Görschwin Fey (Microprocess. Microsystems, 2017)

metaSMT: focus on your application and not on solver integration. - Heinz Riener; Finn Haedicke; Stefan Frehse; Mathias Soeken; Daniel Große; Rolf Drechsler; Görschwin Fey (Int. J. Softw. Tools Technol. Transf., 2017)

Software-Level TMR Approach for On-Board Data Processing in Space Applications. - Karl Janson; Carl Johann Treudler; Thomas Hollstein; Jaan Raik; Maksim Jenihhin; Görschwin Fey (DDECS, 2018)

Augmenting All Solution SAT Solving for Circuits with Structural Information. - Abraham Temesgen Tibebu; Görschwin Fey (DDECS, 2018)

Mining Latency Guarantees for RTL Designs. - Jan Malburg; Heinz Riener; Görschwin Fey (ISMVL, 2018)

Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. - Rolf Drechsler; Christoph Lüth; Görschwin Fey; Tim Güneysu (IVSW, 2018)

Design Understanding: From Logic to Specification*. - Görschwin Fey; Tara Ghasempouri; Swen Jacobs; Gianluca Martino; Jaan Raik; Heinz Riener (VLSI-SoC, 2018)

Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. - Fin Hendrik Bahnsen; Görschwin Fey (DSD, 2019)

Symbolic Circuit Analysis under an Arc Based Timing Model. - Görschwin Fey; Alberto García Ortiz (ETS, 2019)

Syntax-Guided Enumeration of Temporal Properties. - Gianluca Martino; Görschwin Fey (FDL, 2019)

Approximation of Neural Networks for Verification. - Fin Hendrik Bahnsen; Görschwin Fey (MBMV, 2019)

Self-Explaining Digital Systems - Some Technical Steps. - Görschwin Fey; Rolf Drechsler (MBMV, 2019)

Engineering of an Effective Automatic Dynamic Assertion Mining Platform. - Tara Ghasempouri; Jan Malburg; Alessandro Danese; Graziano Pravadelli; Görschwin Fey; Jaan Raik (VLSI-SoC, 2019)

Synthesizing adaptive test strategies from temporal logic specifications. - Roderick Bloem; Görschwin Fey; Fabian Greif; Robert Könighofer; Ingo Pill; Heinz Riener; Franz Röck (Formal Methods Syst. Des., 2019)

Revisiting Explicit Enumeration for Exact Synthesis. - Gianluca Martino; Heinz Riener; Görschwin Fey (DSD, 2020)

Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. - Arne Grünhagen; Julien Branlard; Annika Eichler; Gianluca Martino; Görschwin Fey; Marina Tropmann-Frick (ATS, 2021)

Learning Models of Cyber-Physical Systems using Automata Learning. - Lutz Schammer; Swantje Plambeck; Fin Hendrik Bahnsen; Görschwin Fey (COMPSAC, 2021)

Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. - Gianluca Martino; Arne Grünhagen; Julien Branlard; Annika Eichler; Görschwin Fey; Holger Schlarb (DSD, 2021)

Metrics for the Evaluation of Approximate Sequential Streaming Circuits. - Swantje Plambeck; Gianluca Martino; Görschwin Fey (DSD, 2021)

Designing Recurrent Neural Networks for Monitoring Embedded Devices. - Fin Hendrik Bahnsen; Jan Kaiser; Görschwin Fey (ETS, 2021)

YAPS - Your Open Examination System for Activating and emPowering Students. - Fin Hendrik Bahnsen; Görschwin Fey (ICCSE, 2021)

Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. - Fin Hendrik Bahnsen; Vanessa Klebe; Görschwin Fey (MOCAST, 2021)

Automata Learning for Automated Test Generation of Real Time Localization Systems. - Swantje Plambeck; Jakob Schyga; Johannes Hinckeldeyn; Jochen Kreutzfeldt; Görschwin Fey (CoRR, 2021)

Regression Trees for System Models and Prediction. - Swantje Plambeck; Görschwin Fey (OVERLAY@AI*IA, 2022)

On the Viability of Decision Trees for Learning Models of Systems. - Swantje Plambeck; Lutz Schammer; Görschwin Fey (ASP-DAC, 2022)

Decision Tree Models of Continuous Systems. - Swantje Plambeck; Görschwin Fey (ETFA, 2022)

Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. - Jakob Schyga; Swantje Plambeck; Johannes Hinckeldeyn; Görschwin Fey; Jochen Kreutzfeldt (IPIN, 2022)

Design Understanding: Identifying Instruction Pipelines in Hardware Designs. - Lutz Schammer; Jan Runge; Paula Klimach; Görschwin Fey (MOCAST, 2022)

Self-Explanation in Systems of Systems. - Görschwin Fey; Martin Fränzle; Rolf Drechsler (RE Workshops, 2022)

Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS. - Gianluca Martino; Görschwin Fey (SMACD, 2022)

CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL. - Ahmad Al-Zoubi; Gianluca Martino; Fin Hendrik Bahnsen; Jun Zhu; Holger Schlarb; Görschwin Fey (SOCC, 2022)

Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey. - Arne Grünhagen; Marina Tropmann-Frick; Annika Eichler; Görschwin Fey (BTW, 2023)

DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. - Hany Abdelmaksoud; Zain Alabedin Haj Hammadeh; Görschwin Fey; Daniel Lüdtke (DATE, 2023)

Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. - Swantje Plambeck; Görschwin Fey (DDECS, 2023)

Latency-Optimized Hardware Acceleration of Multilayer Perceptron Inference. - Ahmad Al-Zoubi; Benedikt Schaible; Gianluca Martino; Görschwin Fey (DSD, 2023)

Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. - Leandro Lanzieri; Peter Kietzmann; Görschwin Fey; Holger Schlarb; Thomas C. Schmidt (DSD, 2023)

Data-Based Condition Monitoring and Disturbance Classification in Actively Controlled Laser Oscillators. - Arne Grünhagen; Annika Eichler; Marina Tropmann-Frick; Görschwin Fey (EJC, 2023)

Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems. - Markus Knitt; Swantje Plambeck; Jan Christian Wieck; Julian Kohlisch; Stephan Balduin; Eric M. S. P. Veith; Jakob Schyga; Johannes Hinckeldeyn; Görschwin Fey; Jochen Kreutzfeldt (ETFA, 2023)

FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. - Khaled Galal Abdelwahab Abdelaziz; Ralph Görgen; Görschwin Fey (ETS, 2023)

Informatik für Ingenieure an der Technischen Universität Hamburg. - Bernhard J. Berger; Görschwin Fey (GI-Jahrestagung, 2023)

Enhancing Data Acquisition and Fault Analysis for Large-Scale Facilities: A Case Study on the Laser-Based Synchronization System at the European X-Ray Free-Electron Laser. - Arne Grünhagen; Maximilian Schütte; Annika Eichler; Marina Tropmann-Frick; Görschwin Fey (LWDA, 2023)

GLRP: Guided by Layer-wise Relevance Propagation - Selecting Crucial Neurons in Artificial Neural Networks. - Fin Hendrik Bahnsen; Bernhard J. Berger; Görschwin Fey (MOCAST, 2023)

Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. - Leandro Lanzieri; Lukasz Butkowski; Jirí Král; Görschwin Fey; Holger Schlarb; Thomas C. Schmidt (DSD, 2024)

Usability of Symbolic Regression for Hybrid System Identification - System Classes and Parameters (Short Paper). - Swantje Plambeck; Maximilian Schmidt; Audine Subias; Louise Travé-Massuyès; Görschwin Fey (DX, 2024)

Dynamics-Based Identification of Hybrid Systems using Symbolic Regression. - Swantje Plambeck; Maximilian Schmidt; Görschwin Fey; Audine Subias; Louise Travé-Massuyès (SEAA, 2024)

FaMoS- Fast Model Learning for Hybrid Cyber-Physical Systems using Decision Trees. - Swantje Plambeck; Aaron Bracht; Nemanja Hranisavljevic; Görschwin Fey (HSCC, 2024)

Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction. - Kazi Mohammad Abidur Rahman; Abdelrahman Noshy Abdelalim Ahmed; Görschwin Fey; Ulf Kulau (NorCAS, 2024)

Evaluating the Performance of Large Language Models for Design Validation. - Abdur Rahman; Görschwin Fey (SOCC, 2024)

Usage Driven Relevance Analysis for IP Cores. - Lutz Schammer; Gianluca Martino; Görschwin Fey (SOCC, 2024)

Switching Frequency as FPGA Monitor: Studying Degradation and Ageing Prognosis at Large Scale. - Leandro Lanzieri; Lukasz Butkowski; Jirí Král; Görschwin Fey; Holger Schlarb; Thomas C. Schmidt (CoRR, 2024)

Solving Boolean Problems and Beyond. - Rolf Drechsler; Görschwin Fey (it Inf. Technol., 2024)

Detailed insight into approximate circuits with error-responsive information flow tracking. - Lutz Schammer; Gianluca Martino; Amir Najafi 001; Alberto García Ortiz; Görschwin Fey (it Inf. Technol., 2024)

TUHH-IES/FaMoS-DT: v0.1. - Aaron Bracht; Swantje Plambeck; Görschwin Fey (Zenodo, 2024)

Specification Mining Facing Generative AI. - Görschwin Fey; Harry Foster; Tara Ghasempuri; Badri Gopalan; Jörg Müller 011; Manish Pandey (DATE, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs. - Lutz Schammer; Gianluca Martino; Görschwin Fey (VLSID, 2025)

A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems. - Leandro Lanzieri; Gianluca Martino; Görschwin Fey; Holger Schlarb; Thomas C. Schmidt; Matthias Wählisch (ACM Comput. Surv., 2025)

Data-Driven Probabilistic Evaluation of Logic Properties with PAC-Confidence on Mealy Machines. - Swantje Plambeck; Ali Salamati; Eyke Huellermeier; Görschwin Fey (CoRR, 2025)