Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. - Sidharth Maheshwari; Gourav Modi; Siddhartha 001; Nachiket Kapre (FPL, 2016)

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. - Chethan Kumar H. B; Prashant Ravi; Gourav Modi; Nachiket Kapre (FPGA, 2017)