Reading the footprints of strained islands. - Armando Rastelli; Mathieu Stoffel; G. Katsaros; J. Tersoff; U. Denker; T. Merdzhanova; Gouri Sankar Kar; Giovanni Costantini; K. Kern; H. von Känel (Microelectron. J., 2006)

Morphological evolution and lateral ordering of uniform SiGe/Si(001) islands. - Mathieu Stoffel; Armando Rastelli; T. Merdzhanova; Gouri Sankar Kar; Oliver G. Schmidt (Microelectron. J., 2006)

Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions. - Simon Van Beek; Koen Martens; Philippe Roussel; Gabriele Luca Donadio; Johan Swerts; Sofie Mertens; Gouri Sankar Kar; Tai Min; Guido Groeseneken (IRPS, 2015)

Doped GeSe materials for selector applications. - Naga Sruti Avasarala; Bogdan Govoreanu; Karl Opsomer; Wouter Devulder; Sergiu Clima; Christophe Detavernier; Marleen van der Veen; Jan Van Houdt; Marc Henys; Ludovic Goux; Gouri Sankar Kar (ESSDERC, 2017)

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. - Manu Komalan; Sushil Sakhare; Trong Huynh Bao; Siddharth Rao; Woojin Kim; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor (ISCAS, 2017)

Enhancement of CBRAM performance by controlled formation of a hourglass-shaped filament. - Attilio Belmonte; Ludovic Goux; Jiyong Woo; Umberto Celano; Augusto Redolfi; Sergiu Clima; Gouri Sankar Kar (NVMTS, 2017)

A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. - Raf Appeltans; Praveen Raghavan; Gouri Sankar Kar; Arnaud Furnémont; Liesbet Van der Perre; Wim Dehaene (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. - Manu Komalan; Oh Hyung Rock; Matthias Hartmann; Sushil Sakhare; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor; Sophiane Senni; David Novo; Abdoulaye Gamatié; et al. (DATE, 2018)

Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. - Simon Van Beek; Philippe Roussel; Barry J. O'Sullivan; Robin Degraeve; Stefan Cosemans; Dimitri Linten; Gouri Sankar Kar (ESSDERC, 2018)

Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. - Barry J. O'Sullivan; Simon Van Beek; Philippe J. Roussel; Sidharth Rao; Wonsub Kim; S. Couet; Johan Swerts; Farrukh Yasin; Dimitri Crotti; Dimitri Linten; Gouri Sankar Kar (IRPS, 2018)

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. - Kevin Garello; Kevin Garello Yasin; S. Couet; Laurent Souriau; Johan Swerts; Sidharth Rao; Simon Van Beek; Wonsub Kim; Enlong Liu; Shreya Kundu; Diana Tsvetanova; Kris Croes; et al. (VLSI Circuits, 2018)

SOT-MRAM 300mm integration for low power and ultrafast embedded memories. - Kevin Garello; Farrukh Yasin; S. Couet; Laurent Souriau; Johan Swerts; Sidharth Rao; Simon Van Beek; Wonsub Kim; Enlong Liu; Shreya Kundu; Diana Tsvetanova; N. Jossart; et al. (CoRR, 2018)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. - Lizhou Wu; Siddharth Rao; Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Erik Jan Marinissen; Farrukh Yasin; Sebastien Couet; Said Hamdioui; Gouri Sankar Kar (ETS, 2019)

A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. - Timon Evenblij; Christian Tenllado; Manu Perumkunnil; Francky Catthoor; Sushil Sakhare; Peter Debacker; Gouri Sankar Kar; Arnaud Furnémont; Nicolas Bueno; José Ignacio Gómez Pérez (ICCD, 2019)

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2019)

Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. - Kevin Garello; Farrukh Yasin; Hubert Hody; S. Couet; Laurent Souriau; Shamin H. Sharifi; Johan Swerts; Robert Carpenter; Sidharth Rao; Wonsub Kim; J. Wu; K. K. V. Sethu; et al. (VLSI Circuits, 2019)

Impact of Magnetic Coupling and Density on STT-MRAM Performance. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (DATE, 2020)

Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs. - Simon Van Beek; Barry J. O'Sullivan; Sebastien Couet; Davide Crotti; Dimitri Linten; Gouri Sankar Kar (IRPS, 2020)

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi B. Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2020)

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (ITC, 2020)

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (DATE, 2021)

Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications. - Hyungrock Oh; Attilio Belmonte; Manu Perumkunnil; Jérôme Mitard; Nouredine Rassoul; Gabriele Luca Donadio; Romain Delhougne; Arnaud Furnémont; Gouri Sankar Kar; Wim Dehaene (ESSDERC, 2021)

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. - Sidharth Rao; Woojin Kim; Simon Van Beek; Shreya Kundu; Manu Perumkunnil; Stefan Cosemans; Farrukh Yasin; Sebastien Couet; Robert Carpenter; Barry J. O'Sullivan; Shamin H. Sharifi; N. Jossart; et al. (IMW, 2021)

Threshold switching in a-Si and a-Ge based MSM selectors and its implications for device reliability. - Taras Ravsher; Shamin H. Sharifi; Andrea Fantini; Hubert Hody; Thomas Witters; Daniele Garbin; Robin Degraeve; Valeri Afanas'ev; Jan Van Houdt; Ludovic Goux; D. Crotti; Gouri Sankar Kar (IMW, 2021)

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. - Simon Van Beek; Siddharth Rao; Shreya Kundu; Woojin Kim; Barry J. O'Sullivan; Stefan Cosemans; Farrukh Yasin; Robert Carpenter; Sebastien Couet; Shamin H. Sharifi; Nico Jossart; Davide Crotti; et al. (IRPS, 2021)

Modeling and spectroscopy of ovonic threshold switching defects. - Robin Degraeve; Taras Ravsher; Shoichi Kabuyanagi; Andrea Fantini; Sergiu Clima; Daniele Garbin; Gouri Sankar Kar (IRPS, 2021)

Process-induced charging damage in IGZO nTFTs. - Gaspard Hiblot; Nouredine Rassoul; Lieve Teugels; Katia Devriendt; Adrian Vaisman Chasin; Michiel J. van Setten; Attilio Belmonte; Romain Delhougne; Gouri Sankar Kar (IRPS, 2021)

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (ITC, 2021)

Defect and Fault Modeling Framework for STT-MRAM Testing. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Guilherme Cardoso Medeiros; Moritz Fieback; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Emerg. Top. Comput., 2021)

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. - Mohit Gupta 004; Manu Perumkunnil; Andrea Fantini; Saeideh Alinezhad Chamazcoti; Woojin Kim; Marie Garcia Bardon; Gouri Sankar Kar; Arnaud Furnémont (ESSDERC, 2022)

Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; K. Banerjee; H. Puliyalil; Shreya Kundu; M. Pak; et al. (ICICDT, 2022)

MTJ degradation in SOT-MRAM by self-heating-induced diffusion. - Simon Van Beek; Kaiming Cai; Siddharth Rao; Ganesh Jayakumar; Sebastien Couet; Nico Jossart; Adrian Vaisman Chasin; Gouri Sankar Kar (IRPS, 2022)

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors. - Taras Ravsher; Andrea Fantini; Adrian Vaisman Chasin; Shamin H. Sharifi; Hubert Hody; Harold Dekkers; Thomas Witters; Jan Van Houdt; Valeri Afanas'ev; Sebastien Couet; Gouri Sankar Kar (IRPS, 2022)

Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. - Kaiming Cai; Simon Van Beek; Siddharth Rao; K. Fan; M. Gupta; Van D. Nguyen; Ganesh Jayakumar; Giacomo Talmelli; S. Couet; Gouri Sankar Kar (VLSI Technology and Circuits, 2022)

Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode. - Taras Ravsher; Daniele Garbin; Andrea Fantini; Robin Degraeve; Sergiu Clima; Gabriele Luca Donadio; Shreya Kundu; Hubert Hody; Wouter Devulder; Jan Van Houdt; Valeri Afanas'ev; Romain Delhougne; et al. (VLSI Technology and Circuits, 2022)

Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; S. Sutar; L. Magnarin; Umberto Celano; H. Puliyalil; et al. (VLSI Technology and Circuits, 2022)

Challenges and targets of MRAM-enabled scaled spintronic logic circuits. - Fanfan Meng; Florin Ciubotaru; S.-Y. Lee; Odysseas Zografos; M. Gupta; Van D. Nguyen; Sebastien Couet; Gouri Sankar Kar; Giovanni De Micheli; Christoph Adelmann; I. Asselberghs (CoRR, 2022)

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Computers, 2022)

Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM. - Mahta Mayahinia; Mehdi B. Tahoori; Manu Perumkunnil Komalan; Houman Zahedmanesh; Kristof Croes; Tommaso Marinelli; José Ignacio Gómez Pérez; Timon Evenblij; Gouri Sankar Kar; Francky Catthoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Device-Aware Test for Back-Hopping Defects in STT-MRAMs. - Sicong Yuan; Mottaqiallah Taouil; Moritz Fieback; Hanzhi Xun; Erik Jan Marinissen; Gouri Sankar Kar; Sidharth Rao; Sebastien Couet; Said Hamdioui (DATE, 2023)

Magnetic Domain Wall Memory: A DTCO study for Memory Applications. - M. Gupta; Siddharth Rao; Gouri Sankar Kar; S. Couet (ESSDERC, 2023)

NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2. - Gaspard Hiblot; Taras Ravsher; Roger Loo; Bhuvaneshwari Yengula Venkata Ramana; Nathali Franchina-Vergel; Andrea Fantini; Shamin Houshmand Sharifi; Nina Bazzazian; Kurt Wostyn; Loris Angelo Labbate; Sebastien Couet; Gouri Sankar Kar (ESSDERC, 2023)

Understanding the impact of La dopant position on the ferroelectric properties of hafnium zirconate. - Mihaela Ioana Popovici; Jasper Bizindavyi; Gourab De; Dae Seon Kwon; Gouri Sankar Kar; Jan Van Houdt (ESSDERC, 2023)

Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. - Subhali Subhechha; Stefan Cosemans; Attilio Belmonte; Nouredine Rassoul; Shamin Houshmand Sharifi; Peter Debacker; Diederik Verkest; Romain Delhougne; Gouri Sankar Kar (IMW, 2023)

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs. - L. Panarella; Ben Kaczer; Quentin Smets; Devin Verreck; Tom Schram; Daire Cott; Dennis Lin; Stanislav Tyaginov; I. Asselberghs; Cesar J. Lockhart de la Rosa; Gouri Sankar Kar; Valeri Afanas'ev (IRPS, 2023)

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. - Mohit Kumar Gupta 001; Manu Perumkunnil; Dwaipayan Biswas; Saeideh Alinezhad Chamazcoti; Gouri Sankar Kar; Arnaud Furnémont; Julien Ryckaert (ISCAS, 2023)

The Promise of 2-D Materials for Scaled Digital and Analog Applications. - Devin Verreck; Piet Wambacq; Maarten Van De Put; Zubair Ahmed; Quentin Smets; Aryan Afzalian; Rutger Duflou; Xiangyu Wu; Gioele Mirabelli; Rongmei Chen; Inge Asselberghs; Gouri Sankar Kar (ISSCC, 2023)

Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. - Sicong Yuan; Ziwei Zhang; Moritz Fieback; Hanzhi Xun; Erik Jan Marinissen; Gouri Sankar Kar; Sidharth Rao; Sebastien Couet; Mottaqiallah Taouil; Said Hamdioui (ITC, 2023)

Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT. - Attilio Belmonte; Shreya Kundu; S. Subhechha; Adrian Vaisman Chasin; Nouredine Rassoul; Harold Dekkers; H. Puliyalil; F. Seidel; P. Carolan; Romain Delhougne; Gouri Sankar Kar (VLSI Technology and Circuits, 2023)

Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. - Souvik Ghosh 001; Quentin Smets; S. Banerjee; Tom Schram; Koen Kennes; R. Verheyen; P. Kumar; M.-E. Boulon; Benjamin Groven; H. M. Silva; Shreya Kundu; Daire Cott; et al. (VLSI Technology and Circuits, 2023)

Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach. - Shreya Kundu; D. H. van Doip; Tom Schram; Quentin Smets; S. Banerjee; Benjamin Groven; Daire Cott; Stefan Decoster; P. Bezard; F. Lazzarino; K. Banerjee; Souvik Ghosh 001; et al. (VLSI Technology and Circuits, 2023)

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories. - Saeideh Alinezhad Chamazcoti; Mohit Gupta 004; Hyungrock Oh; Timon Evenblij; Francky Catthoor; Manu Perumkunnil Komalan; Gouri Sankar Kar; Arnaud Furnémont (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hard Error Correction in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Gouri Sankar Kar (ASPDAC, 2024)

Novel Cross-Point Architecture utilizing Distributed Diode Selector for Read Margin Amplification. - Taras Ravsher; Andrea Fantini; Kruti Trivedi; Nouredine Rassoul; Harold Dekkers; Attilio Belmonte; Jan Van Houdt; Valeri Afanas'ev; Kurt Wostyn; Sebastien Couet; Gouri Sankar Kar (IMW, 2024)

Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory. - Taras Ravsher; Robin Degraeve; Daniele Garbin; Sergiu Clima; Andrea Fantini; Gabriele Luca Donadio; Shreya Kundu; Wouter Devulder; Hubert Hody; Goedele Potoms; Jan Van Houdt; Valeri Afanas'ev; et al. (IRPS, 2024)

Light-Assisted Investigation of the Role of Oxygen Flow during IGZO Deposition on Deep Subgap States and their Evolution Under PBTI. - Pietro Rinaudo; Adrian Vaisman Chasin; Ying Zhao; Ben Kaczer; Nouredine Rassoul; Harold Dekkers; Michiel J. van Setten; Attilio Belmonte; Ingrid De Wolf; Gouri Sankar Kar; Jacopo Franco (IRPS, 2024)

Fundamental understanding of NBTI degradation mechanism in IGZO channel devices. - Ying Zhao; Pietro Rinaudo; Adrian Vaisman Chasin; Brecht Truijen; Ben Kaczer; Nouredine Rassoul; Harold Dekkers; Attilio Belmonte; Ingrid De Wolf; Gouri Sankar Kar; Jacopo Franco (IRPS, 2024)

EOT Scaling Via 300mm MX2 Dry Transfer - Steps Toward a Manufacturable Process Development and Device Integration. - S. Ghosh; A. Kruv; Quentin Smets; Tom Schram; D. J. Leech; T. Ding; V. Turkani; Benjamin Groven; A. Dangel; G. Probst; Thomas Uhrmann; Markus Wimplinger; et al. (VLSI Technology and Circuits, 2024)

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. - Farrukh Yasin; A. Palomino; A. Kumar; Valerio Pica; Simon Van Beek; Giacomo Talmelli; Van D. Nguyen; Stefan Cosemans; D. Crotti; Kurt Wostyn; Gouri Sankar Kar; Sebastien Couet (VLSI Technology and Circuits, 2024)

Soft and Hard Error-Correction Techniques in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Valerio Pica; Gouri Sankar Kar (IEEE Des. Test, 2024)

InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM. - Surendra Hemaram; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Tommaso Marinelli; Anita Farokhnejad; Gouri Sankar Kar (DATE, 2025)

Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells. - Daisuke Matsubayashi; Subhali Subhechha; Hyungrock Oh; Nouredine Rassoul; Shamin Houshmand Sharifi; Yiqun Wan; Shreya Kundu; Harinarayanan Puliyalil; Harold Dekkers; Alexandru Pavel; Inhee Lee 004; Gouri Sankar Kar; et al. (IMW, 2025)

Dielectric Breakdown Analysis on Bottom and Top-Gated IGZO-TFT. - Simon Van Beek; Adrian Vaisman Chasin; Subhali Subhechha; Harold Dekkers; Nouredine Rassoul; Yiqun Wan; Hongwei Tang; Joao P. Bastos; Attilio Belmonte; Gouri Sankar Kar (IRPS, 2025)

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. - Fanfan Meng; Siang-Yun Lee; Odysseas Zografos; Mohit Gupta 004; Van D. Nguyen; Giovanni De Micheli; Sorin Cotofana; Inge Asselberghs; Christoph Adelmann; Gouri Sankar Kar; Sebastien Couet; Florin Ciubotaru (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Asymmetric and Adaptive Error Correction in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Tommaso Marinelli; Valerio Pica; Gouri Sankar Kar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)