A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation. - Matthew M. Griffin; Jared Zerbe; Grace Tsang; Michael Ching; Clemenz L. Portmann (IEEE J. Solid State Circuits, 1998)

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. - Jared L. Zerbe; Carl W. Werner; Vladimir Stojanovic; Fred Chen; Jason Wei; Grace Tsang; Dennis Kim; William F. Stonecypher; Andrew Ho; Timothy P. Thrush; Ravi T. Kollipara; Mark A. Horowitz; et al. (IEEE J. Solid State Circuits, 2003)

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. - Vladimir Stojanovic; Andrew Ho; Bruno W. Garlepp; Fred Chen; Jason Wei; Grace Tsang; Elad Alon; Ravi T. Kollipara; Carl W. Werner; Jared L. Zerbe; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)