Reducing the pressure on routing resources of FPGAs with generic logic chains. - Hadi Parandeh-Afshar; Grace Zgheib; Philip Brisk; Paolo Ienne (FPGA, 2011)

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPGA, 2013)

Shadow And-Inverter Cones. - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPL, 2013)

Revisiting and-inverter cones. - Grace Zgheib; Liqun Yang; Zhihong Huang; David Novo; Hadi Parandeh-Afshar; Haigang Yang; Paolo Ienne (FPGA, 2014)

A technology mapper for depth-constrained FPGA logic cells. - Zhenghong Jiang; Grace Zgheib; Colin Yu Lin; David Novo; Zhihong Huang; Liqun Yang; Haigang Yang; Paolo Ienne (FPL, 2015)

Improved carry chain mapping for the VTR flow. - Ana Petkovska; Grace Zgheib; David Novo; Muhsen Owaida; Alan Mishchenko; Paolo Ienne (FPT, 2015)

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components. - Haidar M. Harmanani; Danielle Azar; Grace Zgheib; David Kozhaya (IRI, 2015)

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. - Grace Zgheib; Iyad Ouaiss (J. Circuits Syst. Comput., 2015)

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. - Grace Zgheib; Manana Lortkipanidze; Muhsen Owaida; David Novo; Paolo Ienne (FPGA, 2016)

Automatic wire modeling to explore novel FPGA architectures. - Grace Zgheib; Paolo Ienne (FPT, 2016)

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. - Zhihong Huang; Xing Wei; Grace Zgheib; Wei Li 008; Yu Lin; Zhenghong Jiang; Kaihui Tu; Paolo Ienne; Haigang Yang (FPGA, 2017)

Evaluating FPGA clusters under wide ranges of design parameters. - Grace Zgheib; Paolo Ienne (FPL, 2017)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Leading the Blind - Automated Transistor-Level Modeling for FPGA Architects. - Grace Zgheib (2017)

Finding a Needle in the Haystack of Hardened Interconnect Patterns. - Stefan Nikolic 001; Grace Zgheib; Paolo Ienne (FPL, 2019)

Architectural Enhancements in Intel® Agilex™ FPGAs. - Jeffrey Chromczak; Mark Wheeler; Charles Chiasson; Dana How; Martin Langhammer; Tim Vanderhoek; Grace Zgheib; Ilya Ganusov (FPGA, 2020)

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. - Stefan Nikolic 001; Grace Zgheib; Paolo Ienne (FPGA, 2020)

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. - Stefan Nikolic 001; Grace Zgheib; Paolo Ienne (FPL, 2020)

Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. - Grace Zgheib; Yu Shen Lu; Ilya Ganusov (FPL, 2021)

Detailed Placement for Dedicated LUT-Level FPGA Interconnect. - Stefan Nikolic 001; Grace Zgheib; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2022)

Accelerating Independent Multi-Agent Reinforcement Learning on Multi-GPU Platforms. - Samuel Wiggins; Nikunj Gupta; Grace Zgheib; Mahesh A. Iyer; Viktor K. Prasanna (Euro-Par (3), 2025)

A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. - Mahesh A. Iyer; Andrew B. Kahng; Jason Luu; Bodhisatta Pramanik; Kristofer Vorwerk; Grace Zgheib (FCCM, 2025)

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. - Junius Pun; Xilai Dai; Grace Zgheib; Mahesh A. Iyer; Andrew Boutros; Vaughn Betz; Mohamed S. Abdelfattah (CoRR, 2025)