A study on layout quality of automatic generated cells. - Gracieli Posser; Adriel Ziesemer; Daniel Guimares Jr.; Gustavo Wilke; Ricardo A. L. Reis (ICECS, 2010)

Gate Sizing Minimizing Delay and Area. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (ISVLSI, 2011)

Transistor sizing and gate sizing using geometric programming considering delay minimization. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (NEWCAS, 2012)

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. - Tiago Reimann; Gracieli Posser; Guilherme Flach; Marcelo O. Johann; Ricardo Reis 001 (ISCAS, 2013)

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2013)

A systematic approach for analyzing and optimizing cell-internal signal electromigration. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (ICCAD, 2014)

Analyzing the electromigration effects on different metal layers and different wire lengths. - Gracieli Posser; Vivek Mishra; Ricardo Augusto da Luz Reis; Sachin S. Sapatnekar (ICECS, 2014)

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. - Gracieli Posser; Jozeanne Belomo; Cristina Meinhardt; Ricardo Augusto da Luz Reis (ISVLSI, 2014)

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Impact on performance, power, area and wirelength using electromigration-aware cells. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (ICECS, 2015)

Process variability in FinFET standard cells with different transistor sizing techniques. - Alexandra L. Zimpeck; Cristina Meinhardt; Gracieli Posser; Ricardo Reis 001 (ICECS, 2015)

Reducing the signal Electromigration effects on different logic gates by cell layout optimization. - Gracieli Posser; Lucas de Paris; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (LASCAS, 2015)

Electromigration aware circuits by using special signal non-default routing rules. - Lucas de Paris; Gracieli Posser; Ricardo Reis 001 (ISCAS, 2016)

FinFET cells with different transistor sizing techniques against PVT variations. - Alexandra L. Zimpeck; Cristina Meinhardt; Gracieli Posser; Ricardo Augusto da Luz Reis (ISCAS, 2016)

Reducing the number of transistors with gate clustering. - Calebe Conceição; Gracieli Posser; Ricardo Reis 001 (LASCAS, 2016)

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

ISPD 2018 Initial Detailed Routing Contest and Benchmarks. - Stefanus Mantik; Gracieli Posser; Wing-Kai Chow; Yixiao Ding; Wen-Hao Liu 001 (ISPD, 2018)

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. - Wen-Hao Liu 001; Stefanus Mantik; Wing-Kai Chow; Yixiao Ding; Amin Farshidi; Gracieli Posser (ISPD, 2019)

Challenges and Approaches in VLSI Routing. - Gracieli Posser; Evangeline F. Y. Young; Stephan Held; Yih-Lang Li; David Z. Pan (ISPD, 2022)

Introduction to the Special Section on Advances in Physical Design Automation. - Iris Hui-Ru Jiang; David G. Chinnery; Gracieli Posser; Jens Lienig (ACM Trans. Design Autom. Electr. Syst., 2023)