A 32-bit efficient subpipelined architecture for AES encryption and decryption. - Ke Li; Hua Li; Graeme Mund (CIS, 2022)

A reconfigurable and compact subpipelined architecture for AES encryption and decryption. - Ke Li; Hua Li; Graeme Mund (EURASIP J. Adv. Signal Process., 2023)