The ZS-1 Central Processor. - James E. Smith 001; Gregory E. Dermer; B. D. Vanderwarn; S. D. Klinger; C. M. Rozewski; D. L. Fowler; K. R. Scidmore; James Laudon (ASPLOS, 1987)

The Astronautics ZS-1 processor. - James E. Smith 001; Gregory E. Dermer; B. D. Vanderwarn; S. D. Klinger; C. M. Rozewski; D. L. Fowler; K. R. Scidmore; James Laudon (ICCD, 1988)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. - Peter Hazucha; Tanay Kamik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Greg Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (CICC, 2003)

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)

A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. - Dinesh Somasekhar; Shih-Lien Lu; Bradley A. Bloechel; Greg Dermer; Konrad Lai; Sjeljar Borkar; Vivek De (ESSCIRC, 2005)

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. - Peter Hazucha; Gerhard Schrom; Jaehong Hahn; Bradley A. Bloechel; Paul Hack; Gregory E. Dermer; Siva G. Narendra; Donald S. Gardner; Tanay Karnik; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)