Low-power Networks-on-Chip: Progress and remaining challenges. - Mark Buckler; Wayne P. Burleson; Greg Sadowski (ISLPED, 2013)

Design and implementation of novel source synchronous interconnection in modern GPU chips. - Tao Li; Greg Sadowski (SoCC, 2014)

Reconfigurable Links for Self-Timed On-Chip Communication. - Shomit Das; Greg Sadowski (NoCArc@MICRO, 2016)

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart. - Weiwei Jiang 002; Davide Bertozzi; Gabriele Miorandi; Steven M. Nowick; Wayne P. Burleson; Greg Sadowski (DATE, 2017)

Design and Analysis of an APU for Exascale Computing. - Thiruvengadam Vijayaraghavan; Yasuko Eckert; Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Bradford M. Beckmann; William C. Brantley; Joseph L. Greathouse; Wei Huang 004; Arun Karunanithi; Onur Kayiran; Mitesh R. Meswani; et al. (HPCA, 2017)

Case Study of Process Variation-Based Domain Partitioning of GPGPUs. - Shomit Das; Michael LeBeane; Bradford M. Beckmann; Greg Sadowski (ASYNC, 2018)

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems. - Davide Bertozzi; Gabriele Miorandi; Alberto Ghiribaldi; Wayne P. Burleson; Greg Sadowski; Kshitij Bhardwaj; Weiwei Jiang 002; Steven M. Nowick (IEEE Micro, 2021)