A 19 mW/lane Serdes transceiver for SFI-5.1 application. - Siavash Fallahi; Delong Cui; Deyi Pi; Rose Zhu; Greg Unruh; Marcel Lugthart; Afshin Momtaz (CICC, 2011)

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. - Chang-Hyeon Lee; Lindel Kabalican; Yan Ge; Hendra Kwantono; Greg Unruh; Mark Chambers; Ichiro Fujimori (VLSIC, 2014)

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS. - Massimo Brandolini; Young Shin; Karthik Raviprakash; Tao Wang 010; Rong Wu; Hemasundar Mohan Geddada; Yen-Jen Ko; Yen Ding; Chun-Sheng Huang; Wei-Ta Shih; Ming-Hung Hsieh; Wei-Te Chou; et al. (ISSCC, 2015)

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver. - Jiangfeng Wu; Giuseppe Cusmai; Acer Wei-Te Chou; Tao Wang 010; Bo Shen; Vijayaramalingam Periasamy; Ming-Hung Hsieh; Chun-Ying Chen; Lin He 006; Loke Tan; Aravind Padyana; Cheng-Hsun Yang; et al. (VLSIC, 2015)

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS. - Massimo Brandolini; Young Shin; Karthik Raviprakash; Tao Wang 010; Rong Wu; Hemasundar Mohan Geddada; Yen-Jen Ko; Yen Ding; Chun-Sheng Huang; Wei-Ta Shih; Ming-Hung Hsieh; Wei-Te Chou; et al. (IEEE J. Solid State Circuits, 2015)

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. - Chang-Hyeon Lee; Lindel Kabalican; Yan Ge; Hendra Kwantono; Greg Unruh; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2015)

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (ISSCC, 2016)

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS. - Jiangfeng Wu; Acer Wei-Te Chou; Tianwei Li; Rong Wu; Tao Wang 010; Giuseppe Cusmai; Sha-Ting Lin; Cheng-Hsun Yang; Greg Unruh; Sunny Raj Dommaraju; Mo M. Zhang; Po Tang Yang; et al. (ISSCC, 2016)

A 180 mW multistandard TV tuner in 28 nm CMOS. - Jianhong Xiao; Weinan Gao; Xiaojing Xu; Dave S.-H. Chang; Jiang Cao; Runhua Sun; Vijay Periasamy; Ning-Yi Wang; Xi Chen 027; Greg Unruh; Takayuki Hayashi; Tai-Hong Chih; et al. (VLSI Circuits, 2016)

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. - Jiangfeng Wu; Giuseppe Cusmai; Acer Wei-Te Chou; Tao Wang 010; Bo Shen; Vijayaramalingam Periasamy; Ming-Hung Hsieh; Chun-Ying Chen; Lin He 006; Loke Kun Tan; Aravind Padyana; Vincent Cheng-Hsun Yang; et al. (IEEE J. Solid State Circuits, 2016)

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2017)

A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS. - Chi-Hung Lin; Jackie Koon Lun Wong; Tae-Youn Kim; Guangxi Ray Xie; Donald Major; Greg Unruh; Sunny Raj Dommaraju; Hans Eberhart; Ardie G. Venes (ISSCC, 2018)