A universal MOSFET mobility degradation model for circuit simulation. - Gregory Munson Yeric; A. F. Tasch Jr.; Sanjay K. Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Universal MOSFET hole mobility degradation models for circuit simulation. - Victor Martin Agostinelli Jr.; Gregory Munson Yeric; A. F. Tasch Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Improved universal MOSFET electron mobility degradation models for circuit simulation. - C. Patrick Yue; Victor Martin Agostinelli Jr.; Gregory Munson Yeric; A. F. Tasch Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. - Greg Yeric; Ethan Cohen; John Garcia; Kurt Davis; Esam Salem; Gary Green (IEEE Des. Test Comput., 2005)

Making Manufacturing Work For You. - Srikanth Venkataraman; Ruchir Puri; Steve Griffith; Ankush Oberai; Robert Madge; Greg Yeric; Walter Ng; Yervant Zorian (DAC, 2007)

Correlating models and silicon for improved parametric yield. - Rob Aitken; Greg Yeric; David Flynn (DATE, 2011)

Exploring sub-20nm FinFET design with predictive technology models. - Saurabh Sinha; Greg Yeric; Vikas Chandra; Brian Cline; Yu Cao 001 (DAC, 2012)

Design benchmarking to 7nm with FinFET predictive technology models. - Saurabh Sinha; Brian Cline; Greg Yeric; Vikas Chandra; Yu Cao 001 (ISLPED, 2012)

The past present and future of design-technology co-optimization. - Greg Yeric; Brian Cline; Saurabh Sinha; David Pietromonaco; Vikas Chandra; Rob Aitken (CICC, 2013)

Physical design and FinFETs. - Robert C. Aitken; Greg Yeric; Brian Cline; Saurabh Sinha; Lucian Shifren; Imran Iqbal; Vikas Chandra (ISPD, 2014)

Design, technology and yield in the post-moore era. - Greg Yeric (ITC, 2014)

Power benefit study of monolithic 3D IC at the 7nm technology node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2015)

Circuit design perspectives for Ge FinFET at 10nm and beyond. - Saurabh Sinha; Lucian Shifren; Vikas Chandra; Brian Cline; Greg Yeric; Robert C. Aitken; Bingjie Cheng; Andrew R. Brown; Craig Riddet; C. Alexandar; Campbell Millar; Asen Asenov (ISQED, 2015)

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. - Xiaoqing Xu; Brian Cline; Greg Yeric; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Match-making for monolithic 3D IC: finding the right technology node. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (DAC, 2016)

At the core of system scaling. - Greg Yeric (ESSCIRC, 2016)

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Raney Southerland; Michael Doherty; Greg Yeric; Sung Kyu Lim (ICCAD, 2016)

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. - Kwang Min Kim; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2016)

Monolithic 3D IC design: Power, performance, and area impact at 7nm. - Kartik Acharya; Kyungwook Chang; Bon Woong Ku; Shreepad Panth; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISQED, 2016)

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. - Robert C. Aitken; Vikas Chandra; Brian Cline; Shidhartha Das; David Pietromonaco; Lucian Shifren; Saurabh Sinha; Greg Yeric (IET Comput. Digit. Tech., 2016)

ASAP7: A 7-nm finFET predictive process design kit. - Lawrence T. Clark; Vinay Vashishtha; Lucian Shifren; Aditya Gujja; Saurabh Sinha; Brian Cline; Chandarasekaran Ramamurthy; Greg Yeric (Microelectron. J., 2016)

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha; Brian Cline; Greg Yeric (ICCAD, 2017)

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. - Jiaojiao Ou; Xiaoqing Xu; Brian Cline; Greg Yeric; David Z. Pan (ICCD, 2017)

Frequency and time domain analysis of power delivery network for monolithic 3D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2017)

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha; Brian Cline; Greg Yeric (CoRR, 2018)

IC Design After Moore's Law. - Greg Yeric (CICC, 2019)

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. - Saurabh Sinha; Xiaoqing Xu; Mudit Bhargava; Shidhartha Das; Brian Cline; Greg Yeric (CoRR, 2020)

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. - Chi-Shuen Lee; Brian Cline; Saurabh Sinha; Greg Yeric; H.-S. Philip Wong (CoRR, 2021)

Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology. - Saurabh V. Suryavanshi; Greg Yeric; Max Irby; X. M. Henry Huang; Glen Rosendale; Lucian Shifren (IMW, 2022)

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)